HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 210

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
210 of 272
Table 9.4: Memory address calculation for DTMF coefficients related to equation ( 9.3)
base address
frequency offset
(1
(2
channel offset
W-byte offset
×Ø
Ò
harmonic)
harmonic)
RAM size
low tones
high byte
low byte
number
1209 Hz
1336 Hz
1477 Hz
1633 Hz
Ï
697 Hz
770 Hz
852 Hz
941 Hz
DTMF controller
Æ
32k
Data Sheet
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
½
0x1000
address
0x200
0x100
0x180
0x280
0x300
0x380
offset
offset
0x0C
0x1C
0x2C
0x3C
offset
0x00
0x80
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0
1
high tones
RAM size
high byte
low byte
number
1406 Hz
1555 Hz
1704 Hz
1882 Hz
2418 Hz
2672 Hz
2954 Hz
3266 Hz
128k
512k
Ï
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Æ
0x2000
0x2000
address
0x1C0
0x2C0
0x3C0
0x240
0x140
0x340
offset
0xC0
offset
0x4C
0x5C
0x6C
0x7C
offset
0x40
0x40
0x44
0x48
0x50
0x54
0x58
0x60
0x64
0x68
0x70
0x74
0x78
March 2003 (rev. A)
3
2
Cologne
Chip