HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 52

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
Register Name
PMC
PMCSR
specification compatibility.
52 of 272
¾
: D3_cold support is implemented but must be set in the EEPROM configuration data.
: Changing the power management does not change the power dissipation. It is only implemented for PCI
Address
0x42
0x44
Universal external bus interface
Width
Word
Word
Table 2.8: PCI configuration registers
Default Value
Data Sheet
0x7E22
0x0000
Remarks
Power Management Capabilities, see also
‘PCI Bus Power Management Interface
Specification Rev. 1.1’.This register’s value
can be set by EEPROM. Base address for
configuration write is 0xE0.
Bits
0..2
3
4
5
8..6
9
10
15..11
Power Management Control/Status
Bits
1..0
7..2
8
14..9
15
Function
PowerState: These bits are used both to
determine the current power state of a
function and to set the function into a new
power state
’00’: D0
’01’: D1
’10’: D2
’11’: D3_hot
fixed to ’0’
PME_En:
’1’ enables the function to assert PME.
’0’ = PME assertion is disabled.
fixed to 0
PME_Status: This bit is set when the
function would normally assert the PME
signal independent of the state of the
PME_En bit.
Writing a ’1’ to this bit will clear it and
cause the function to stop asserting a
PME (if enabled).
Writing a ’0’ has no effect.
Function
’010’ = PCI Power Management Spec.
Version 1.1.
’0’ = The HFC-E1 does not require PCI-
clock to generate PME.
Fixed to ’0’.
’1’ = Device specific initialisation is re-
quired.
’000’ = No D3_cold support
’1’ = Supports D1 Power Management
State
’1’ = Supports D2 Power Management
State
PME can be asserted from D0, D1, D2
and D3_hot.
(continued from previous page)
¾
¾
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.
¾
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March 2003 (rev. A)
Cologne
Chip
.