HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 232

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
232 of 272
R_BRG_TIM_SEL45
Timing selection for bridge device connected to /BRG_CS4 and /BRG_CS5
Every selection uses a timing defined in R_BRG_TIM0 . . . R_BRG_TIM3.
1..0
3..2
5..4
7..6
R_BRG_TIM_SEL67
Timing selection for bridge device connected to /BRG_CS6 and /BRG_CS7
Every selection uses a timing defined in R_BRG_TIM0 . . . R_BRG_TIM3.
1..0
3..2
5..4
7..6
Bits
Bits
0
0
0
0
0
0
0
0
Reset
Value
Reset
Value
Name
V_BRG_WR_SEL4
V_BRG_RD_SEL4
V_BRG_WR_SEL5
V_BRG_RD_SEL5
Name
V_BRG_WR_SEL6
V_BRG_RD_SEL6
V_BRG_WR_SEL7
V_BRG_RD_SEL7
Clock, reset, interrupt, timer and watchdog
(write only)
(write only)
Data Sheet
RD-timing selection for the chip connected to
RD-timing selection for the chip connected to
RD-timing selection for the chip connected to
RD-timing selection for the chip connected to
Description
WR-timing selection for the chip connected to
pin /BRG_CS4
pin /BRG_CS4
WR-timing selection for the chip connected to
pin /BRG_CS5
pin /BRG_CS5
Description
WR-timing selection for the chip connected to
pin /BRG_CS6
pin /BRG_CS6
WR-timing selection for the chip connected to
pin /BRG_CS7
pin /BRG_CS7
March 2003 (rev. A)
Cologne
Chip
0x4E
0x4F