HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 75

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.5.2.4 16 bit processors in mode 4 (Intel, multiplexed)
16 bit processors can either read data with byte or word access. Only 8 bit are used for
address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A word read is shown in Figure 2.15. FIFO and
16 bit width alternatively. The 16 bit processor must support byte access because all other
register read accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the data bus D15 . . . D0 from
tristate into data driven state (see Table 2.22 on page 77).
In mode 4 (Intel, multiplexed) the states
must be fulfilled to drive data out. The data bus is stable after
after
Address and /BE require a setup time
these lines is
address write is not required.
An 8 bit read access (low byte) is performed in the same way as it is done with 8 bit proces-
sors. Thus see Figure 2.13 for the timing specification.
March 2003 (rev. A)
HFC-E1
AD[31:16]
/RD+/CS
AD[15:8]
/BE[3:2]
/BE[1:0]
AD[7:0]
/WR
ALE
Ø
À
Figure 2.15: Word read access from 16 bit processors in mode 4 (Intel, multiplexed)
.
Ø
/BE
À
t
address
ALE
. If two consecutive read accesses are on the same address, multiple register
byte enable
t
AS
address
t
’0’
AH
t
and
ALEH
Universal external bus interface
´
/RD
Ø
Ë
Data Sheet
t
word read access
RDmin
·
which starts with the
t
t
DRDZ
permanently high
permanently high
RD
/CS
data
data
µ
’0’
t
- / -counter read access have 8 bit or
DRDH
and
Ø
t
CYCLE
Ñ Ò
/WR
of ALE. The hold time of
and returns into tristate
word read access
t
RDmin
t
t
DRDZ
RD
’1’
data
data
Cologne
Chip
t
DRDH
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