HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 64

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
The processor interface mode is selected by MODE0
addresses (A0 . . . A7) are used for addressing the internal registers of the HFC-E1 directly
by their address.
In processor interface mode some user data can be stored in the EEPROM (see Section 2.1.1
for details).
2.5.1 Parallel processor interface modes
The HFC-E1 has 3 different parallel processor interface modes. Due to name compatibility
with other chips of the HFC series the processor interface modes are numbered 2 . . . 4 like
shown in Table 2.16.
Processor interface modes 2 and 3 use separate lines for address and data. These two modes
are selected by ALE. This pin must have a fixed level and should be directly connected to
ground or power supply. Mode 4 has multiplexed address / data lines. The address is latched
from lines D7 . . . D0 with the falling edge of ALE.
The processor interface mode is determined during hardware reset time (pin RESET). For
modes 2 and 3 the ALE pin must have the appropriate level. Mode 4 is selected after reset
with the first rising edge of ALE. The HFC-E1 then switches permanently from mode 2 or
mode 3 into mode 4. The HFC-E1 cannot switch to mode 4 until end of reset time. Rising
and falling edges of ALE are ignored during reset time.
ALE must be stable after reset except in processor interface mode 4.
2.5.2 Signal and timing characteristics
Table 2.17 shows the interface signal levels for the different processor interface modes. Tim-
ing characteristics are shown in Figures 2.9 to 2.12 for mode 2 and mode 3. Figures 2.13
to 2.18 show mode 4 timing characteristics. Please see Table 2.18 for a quick timing and
symbol list finding.
In processor interface mode 4 it is possible to access byte, word or double word on the lines
AD31 . . . AD0. Due to the multiplexed lines the PCI pin names are used in this case. In
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Number
Table 2.16: Pins and signal names of the HFC-E1 processor interface modes
HFC-E1 pins
20
21
22
24
Name
/CS
/IOR
/IOW
ALE
Universal external bus interface
Mode 2
(Motorola)
Non-multiplexed
/CS
/DS
R/W
’1’
Data Sheet
Signal names
(Intel)
/RD
Mode 3
Non-multiplexed
/CS
/WR
’0’
½
and MODE1
(Intel)
Mode 4
Multiplexed
/CS
/RD
/WR
ALE
March 2003 (rev. A)
¼
. Then 256 I/O
Cologne
Chip