HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 216

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
10.4 Read only register
216 of 272
R_BERT_STA
Bit error rate test status
3..0
4
5
7..6
R_BERT_ECL
BERT error counter, low byte
7..0
Bits
Bits
0
0
0
0
0
Reset
Value
Reset
Value
Name
(reserved)
V_BERT_SYNC
V_BERT_INV_DATA
(reserved)
Name
V_BERT_ECL
(read only)
(read only)
Data Sheet
BERT
Bits 7 . . . 0 of the BERT error counter
Description
BERT synchronization status
’0’ = BERT not synchronized to input data
’1’ = BERT sync to input data
BERT data inversion
’0’ = BERT receives normal data
’1’ = BERT receives inverted data
Description
This register should be read first to ‘lock’ the value
of the R_BERT_ECH register until
R_BERT_ECH has also been read.
Note: The BERT counter is cleared after reading
this register.
March 2003 (rev. A)
Cologne
Chip
0x1A
0x17