HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 169

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

5.4.2 Read only register
March 2003 (rev. A)
HFC-E1
R_STATE
E1 state machine register
2..0
5..3
6
7
Bits
0
0
0
Value
Reset
V_E1_STA
Name
(reserved)
V_ALT_FR_RX
V_ALT_FR_TX
E1 interface
(read only)
Data Sheet
Description
E1 state
Binary value of actual state (LT: Gx, TE: Fx).
Alternating RAM bank
Shows which bank of time slot 0 data in RAM is
currently used for receive data. Receive data is
written to the RAM.
This bit is toggled with every multiframe.
Alternating RAM bank
Shows which bank of time slot 0 data in RAM is
currently used for transmit data. Transmit data is
read from the RAM.
This bit is toggled with every multiframe.
Cologne
Chip
169 of 272
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