HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 21

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

1.2 Features
March 2003 (rev. A)
HFC-E1
1
2
3
Mitel Serial Telecom bus
All
Never connect the power supply of the HFC-E1 to 5 V!
integrated E1 interface
single chip ISDN-E1 controller with HDLC support for all B- and D-channels
full I.431 ITU E1 ISDN support in TE , NT and LT mode
32 independent read and write HDLC channels for e.g. 30 ISDN B-channels, 1 ISDN
D-channel
B-channel transparent mode independently selectable
up to 32 FIFOs for transmit and for receive data, FIFO sizes are configurable
each FIFO can be assigned to an arbitrary HFC-channel, moreover each HFC-channel
can be assigned to a time slot of the E1 interface or to a time slot of the PCM interface
max. 31 HDLC frames (with 128 kByte or 512 kByte external RAM) or 15 HDLC
frames (with 32 kByte build-in RAM) per FIFO
1 . . . 8 bit processing for subchannels selectable
B-channels for higher data rate can be combined up to 256 bit
PCM128 / PCM64 / PCM30 interface configurable to interface MST
Siemens IOM2
chip connection or external CODECs
Switch matrix for PCM included
H.100 data rate supported
integrated ISA Plug and Play interface with buffers for ISA-databus
integrated PCMCIA interface
integrated PCI bus interface (Spec. 2.2) for 3.3 V and 5 V signal environment
microprocessor interface compatible to Motorala bus and Siemens / Intel bus
Serial processor interface (SPI)
multiparty audio conferences switchable
DTMF detection on all 32 channels
Timer and watchdog with interrupt capability
CMOS technology 3.3 V (5 V tolerant on nearly all inputs
PQFP 208 package
TM
marked names are registered trademarks of the appropriate organizations.
TM
and Motorola GCI
General description
Data Sheet
TM
2
(no monitor or C/I-channel support) for inter
3
)
TM
(MVIP
Cologne
Chip
21 of 272
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)
1
or