HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 115

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

The default subchannel configuration of the register A_SUBCH_CFG leads to a transparent
behavior. That means, only complete data bytes are transmitted in receive and transmit
direction.
3.5.1 Transparent mode
In transparent mode every FIFO has a data rate of 8 kByte/s. Every 125 s one byte of a
FIFO is processed. The subchannel processor takes only the bits that are defined by the
FIFO parameters and inserts them into the channel mask A_CH_MSK.
Received HFC-channel data bytes are stored completely in the FIFO and are independently
from the V_BIT_CNT and V_START_BIT settings.
Simple Mode
As the FIFO and HFC-channel numbers are the same in Simple Mode, only one FIFO can
be connected to a HFC-channel. Subchannel processing can do nothing more than mask out
some bits of every transmitted data byte.
Suppose FIFO[
V_START_BIT
the HFC-channel data bytes as shown in Table 3.5. From every FIFO byte only three bits are
transmitted to the HFC-channel. These bits are accentuated in the table. The other bits are
defined by the channel mask.
In receive direction, the subchannel processor has no effect in Simple mode combined with
transparent mode. So received HFC-channel bytes are stored in the FIFO without changing.
Channel Select Mode
In Channel Select Mode it is possible to connect more than one FIFO to a HFC-channel.
The configuration in Figure 3.11 with three FIFOs can be taken as example. The bit extrac-
tion / insertion units must be configured with the following register settings:
March 2003 (rev. A)
HFC-E1
Å
G
Typically, the R_FIFO register contains always an FIFO index. There
is one exception where the R_FIFO value has a different meaning: The
HFC-channel mask byte is programmed by writing the HFC-channel into
the R_FIFO register.
G
The A_CH_MSK array register is indexed by R_FIFO to write the mask
byte. However the mask is assigned to a HFC-channel, namely that HFC-
channel which is assigned to the indexing FIFO.
Å
¼
Important !
Important !
. Then the FIFO[
Ñ
,TX] has the register A_SUBCH_CFG settings V_BIT_CNT
¾
(see Fig. 3.11). Further, the channel mask is defined as A_CH_MSK
Ñ
,TX] data bytes
Data Sheet
Data flow
Ñ ½
. . .
Ñ
with bit index
¼
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Chip
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