HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 136

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Cologne
HFC-E1
FIFO handling and HDLC controller
Chip
4.3.4 FIFO full condition in HDLC receive HFC-channels
Because of the E1 time slots not having a hardware based flow control there is no possibility
to stop input data if a receive FIFO is full.
Thus there is no FIFO full condition implemented in the HFC-E1. The HFC-E1 assumes
that the FIFOs are deep enough that the host processor’s hardware and software is able to
avoid any overflow of the receive FIFOs. Overflow conditions are again more than 31 input
frames (resp. 15 frames with 32k RAM) or a memory overflow of the FIFO because of
excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are
sent without software intervention. Due to the great size of the HFC-E1 FIFOs it is easy
to poll the HFC-E1 even in large time intervalls without having to fear a FIFO overflow
condition.
½
¾
To avoid any undetected FIFO overflows the software driver should check
, i.e. the
½
¾
number of frames in the FIFO. If
is less than the number in the last reading, an
overflow took place if there was no reading of a frame in between.
After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset
bit V_RES_F in the register R_INC_RES_FIFO.
4.3.5 Transparent mode of the HFC-E1
It is possible to switch off the HDLC operation for each FIFO independently by the bit
V_HDLC_TRP in register A_CON_HDLC. If this bit is set, data from the FIFO is sent
directly to the E1 or PCM bus interface and data from the E1 or PCM bus interface is sent
directly to the FIFO.
½
¾
Be sure to switch into transparent mode only if
. Being in transparent mode the
½
¾
-counters remain unchanged.
and
are the input and output pointers respectively.
½
¾
Because
, the -counters are always accessable and have valid data for FIFO input
and output.
If a transmit FIFO changes to FIFO empty condition no CRC is generated and the last data
byte written into the FIFO is repeated until there is new data.
Normally the last byte is undefined because of the -counter pointing to a previously unwrit-
ten address. To define the last byte, the last write access to the FIFO must be done without
increment (see register A_FIFO_DATA0_NOINC).
In receive HFC-channels there is no check on flags or correct CRCs and no status byte added.
Unlike in HDLC mode, where byte synchronization is achieved with HDLC flags, the byte
boundaries are not arbitrary. The data is just the same as it comes from or is sent to the E1
or PCM bus interface.
Transmit and receive transparent data can be done in two ways. The usual way is transporting
FIFO data to the E1 interface with the LSB first as usual in HDLC mode. The second way is
transmitting the bytes in reverse bit order as usual for PCM data. So the first bit is the MSB.
The bit order can be reversed by setting bit V_REV of the register R_FIFO when the FIFO
is selected.
136 of 272
Data Sheet
March 2003 (rev. A)