HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 66

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
2.5.2.1 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
/DS+/CS
/RD+/CS
8 bit processors read data like shown in Figure 2.9. Timing values are listed in Table 2.20.
/BE3 . . . /BE1 must always be ’1’. /BE0 can be fixed to ’0’ or must be low during access to
switch the data bus D7 . . . D0 from tristate into data driven state.
Data can be read in mode 2 (Motorola) with
In mode 3 (Intel, non-multiplexed) the states
must be fulfilled to drive data out. The data bus is stable after
after
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/BE[3:1]
D[15:8]
A[7:0]
D[7:0]
2
/BE0
R/W
/WR
/DS
Ø
·
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
/CS means logical OR function of the two signals.
Figure 2.9: Read access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
À
.
/BE0
/BE0
byte read access
t
AS
’0’
’0’
t
RWS
t
RDmin
address
t
DRDZ
t
RD
and
and
Universal external bus interface
data
t
t
t
AH
DRDH
RWH
´
´
/DS
/RD
Data Sheet
·
permanently tristate
·
permanently high
permanently high
permanently low
/CS
2
/CS
µ
µ
’0’
t
CYCLE
’0’
and
and
byte read access
Ø
t
AS
Ñ Ò
R/W
t
RWS
t
/WR
RDmin
address
t
DRDZ
and returns into tristate
t
RD
March 2003 (rev. A)
data
’1’
’1’
t
t
t
AH
DRDH
RWH
Cologne
Chip