HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 240

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
12.5.2 Read only register
240 of 272
R_IRQ_OVIEW
FIFO interrupt overview register
Every bit with value ’1’ indicates that an interrupt has occured in the FIFO block.
A FIFO block consists of 4 transmit and 4 receive FIFOs. The exact FIFO can be
determined by reading the R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 registers that
belong to the specified FIFO block.
Reading any R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 registers clear the cor-
responding bit in this register. Reading this overview register does not clear any
interrupt bit.
0
1
2
3
4
5
6
7
Bits
Reset
Value
Name
V_IRQ_FIFO_BL0
V_IRQ_FIFO_BL1
V_IRQ_FIFO_BL2
V_IRQ_FIFO_BL3
V_IRQ_FIFO_BL4
V_IRQ_FIFO_BL5
V_IRQ_FIFO_BL6
V_IRQ_FIFO_BL7
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Interrupt overview of FIFO block 0
Interrupt overview of FIFO block 1
Interrupt overview of FIFO block 2
Interrupt overview of FIFO block 3
Interrupt overview of FIFO block 4
Interrupt overview of FIFO block 5
Interrupt overview of FIFO block 6
Interrupt overview of FIFO block 7
Description
(FIFOs 0 . . . 3)
(FIFOs 4 . . . 7)
(FIFOs 8 . . . 11)
(FIFOs 12 . . . 15)
(FIFOs 16 . . . 19)
(FIFOs 20 . . . 23)
(FIFOs 24 . . . 27)
(FIFOs 28 . . . 31)
March 2003 (rev. A)
Cologne
Chip
0x10