HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 126

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
126 of 272
A_SUBCH_CFG [FIFO]
Subchannel parameters for bit processing of the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
Note: For D-channel this register must be 0x02.
2..0
5..3
6
7
Bits
G
A FIFO is disabled if V_HDLC_TRP
A_CON_HDLC[FIFO]. This setting is useful to reduce RAM accesses if
a FIFO is not used at all.
If HFC-channel data is routed through the switches of the flow controller
(Fig. 3.3 and 3.4) the FIFO must be enabled. That applies to all connec-
tions except the PCM-to-PCM data transmission.
0
0
0
0
Reset
Value
Important !
Name
V_BIT_CNT
V_START_BIT
V_LOOP_FIFO
V_INV_DATA
(write only)
Data Sheet
Data flow
Bit counter for HDLC and transparent mode
Start bit for HDLC and transparent mode
FIFO loop
Description
This bitmap contains the number of bits to be
processed.
’000’ = process 8 bits (64 kbit/s)
’001’ = process 1 bit (8 kbit/s)
’010’ = process 2 bits (16 kbit/s)
’011’ = process 3 bits (24 kbit/s)
’100’ = process 4 bits (32 kbit/s)
’101’ = process 5 bits (40 kbit/s)
’110’ = process 6 bits (48 kbit/s)
’111’ = process 7 bits (56 kbit/s)
’000’ = start processing with bit 0
’001’ = start processing with bit 1
’010’ = start processing with bit 2
’011’ = start processing with bit 3
’100’ = start processing with bit 4
’101’ = start processing with bit 5
’110’ = start processing with bit 6
’111’ = start processing with bit 7
’0’ = normal operation
’1’ = repeat current frame (in transparent mode
only)
Inverted data
’0’ = normal data out
’1’ = inverted data out
·
V_TRP_IRQ
¼
in the register
March 2003 (rev. A)
Cologne
Chip
0xFB