HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 142

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
(See Table 4.3 for reset value.)
142 of 272
A_F12 [FIFO]
FIFO input HDLC frame counter
Before reading this array register the FIFO must be selected by the register R_FIFO.
7..0
R_INT_DATA
Internal data register
This register can be read to access data with short read signal.
7..0
Bits
Bits
Reset
Value
Reset
Value
Name
V_F1
Name
V_INT_DATA
FIFO handling and HDLC controller
½
(read only)
(read only)
Data Sheet
Bits [7..0] are counter value of ½ and bits
Internal data buffer
Description
[15..8] are counter value of ¾
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
Description
March 2003 (rev. A)
Cologne
Chip
0x0C
0x88