HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 86

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
2.7 Register description
2.7.1 Write only registers
(For reset group description see Table 12.4 on page 235.)
86 of 272
R_CIRM
Interrupt and reset register
2..0
3
4
5
6
7
Bits
0
0
0
0
0
0
Reset
Value
Name
V_IRQ_SEL
V_SRES
V_HFCRES
V_PCMRES
V_E1RES
V_RLD_EPR
Universal external bus interface
(write only)
Data Sheet
IRQ channel selection in ISA PnP mode
Description
’000’ = interrupt lines disable
’001’ = IRQ0
’010’ = IRQ1
’011’ = IRQ2
’100’ = IRQ3
’101’ = IRQ4
’110’ = IRQ5
’111’ = IRQ6
Soft reset
This reset is similar to the hardware reset. The
selected I/O address (CIP) remains unchanged. The
reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
HFC-reset
Sets all FIFO and HDLC registers to their initial
values. The reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
PCM reset
Sets all PCM registers to their initial values. The
reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
E1-reset
Sets all E1 interface registers to their initial values.
The reset is active until the bit is cleared.
’0’ = deactivate reset
’1’ = activate reset
EEPROM reload
’0’ = normal operation
’1’ = reload EEPROM to SRAM
This bit must be cleared by software. The reload is
started when the bit is cleared.
March 2003 (rev. A)
Cologne
Chip
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