HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 73

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.5.2.3 8 bit processors in mode 4 (Intel, multiplexed)
8 bit processors read data like shown in Figure 2.13. Timing values are listed in Table 2.23.
/BE3 . . . /BE1 must always be ’1’. /BE0 can be fixed to ’0’ or must be low during access to
switch the data bus D7 . . . D0 from tristate into data driven state.
Data can be read in mode 4 (Intel, multiplexed) with
The data bus is stable after
Address and /BE0 (if not fixed to low) require a setup time
ALE. The hold time of these lines is
address, multiple register address write is not required.
March 2003 (rev. A)
HFC-E1
/RD+/CS
AD[31:8]
/BE[3:1]
AD[7:0]
3
/BE0
/WR
ALE
/RD
·
/CS means logical OR function of the two signals.
Figure 2.13: Read access from 8 bit processors in mode 4 (Intel, multiplexed)
/BE0
t
address
ALE
t
AS
address
t
’0’
AH
Ø
t
ALEH
and
Universal external bus interface
Ñ Ò
and returns into tristate after
´
/RD
Ø
À
t
byte read access
Data Sheet
RDmin
. If two consecutive read accesses are on the same
·
t
t
DRDZ
permanently high
permanently high
RD
permanently low
/CS
data
µ
’0’
3
t
DRDH
and
Ø
t
CYCLE
Ë
Ø
/WR
which starts with the
À
t
byte read access
RDmin
.
t
t
DRDZ
RD
’1’
data
Cologne
Chip
t
DRDH
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