HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 11

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

List of Tables
March 2003 (rev. A)
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10 ISA address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 ISA Plug and Play registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 Overview of the PCMCIA interface pins . . . . . . . . . . . . . . . . . . . . . . . .
2.13 PCMCIA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Overview of the parallel processor interface pins in mode 2 and 3 . . . . . . . . . . .
2.15 Overview of the processor interface pins in mode 4 . . . . . . . . . . . . . . . . . .
2.16 Pins and signal names of the HFC-E1 processor interface modes . . . . . . . . . . .
2.17 Overview of read and write accesses in processor interface mode . . . . . . . . . . .
2.18 Timing diagrams of the parallel processor interface . . . . . . . . . . . . . . . . . .
2.19 Data access width in mode 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.20 Symbols of read accesses in Figures 2.9 and 2.11 . . . . . . . . . . . . . . . . . . .
2.21 Symbols of write accesses in Figures 2.10 and 2.12 . . . . . . . . . . . . . . . . . .
2.22 Data access width in mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.23 Symbols of read accesses in Figures 2.13, 2.15 and 2.17 . . . . . . . . . . . . . . . .
2.24 Symbols of write accesses in Figures 2.14, 2.16 and 2.18 . . . . . . . . . . . . . . .
2.25 Overview of the SPI interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
Overview of the HFC-E1 bus interface registers . . . . . . . . . . . . . . . . . . . .
Access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of common bus interface pins . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM load size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRAM start address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the PCI interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI command types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the ISA PnP interface pins . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the HFC-E1 data flow registers . . . . . . . . . . . . . . . . . . . . . .
Flow controller connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V_DATA_FLOW programming values for single-destination connections . . . . . .
List specification of the example in Figure 3.10 . . . . . . . . . . . . . . . . . . . . 112
Subchannel processing example in SM combined with transparent mode . . . . . . . 116
Subchannel processing example in CSM combined with transparent mode . . . . . . 116
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