HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 46

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
If no EEPROM is used, pin EE_SCL/EN must be connected to ground while EE_SDA
must remain open as shown in Figure 2.2.
2.1.3 Register access
In PCI I/O mapped mode, ISA PnP, PCMCIA mode and SPI mode all registers are selected
by writing the register address into the Control Internal Pointer (CIP) register. This is done
by writing the CIP on the higher I/O addresses (AD2, SA2, A2,
can also be read with AD2, SA2, A2,
All consecutive read or write data accesses (AD2, SA2, A2,
selected register until the CIP register is changed.
In processor interface mode all internal registers can be directly accessed. The registers are
selected by A0 . . . A7.
In PCI mode internal A0 and A1 are generated from the byte enable lines.
2.1.4 RAM access
The SRAM of the HFC-E1 can be accessed by the host. For doing so the desired RAM
address has to be written in the R_RAM_ADDR0 . . . R_RAM_ADDR2 registers first. Then
data can be read / written by reading / writing the register R_RAM_DATA. An automatic
increment function can be set in the register R_RAM_ADDR2.
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See sections 2.2 to 2.6 for overview tables of the interface specific pins.
Figure 2.2: EE _ SCL/EN and EE _ SDA connection without EEPROM
U1
HFC-E1
EE_SLC/EN
EE_SDA
Figure 2.1: EEPROM connection circuitry
Universal external bus interface
102
103
U1
HFC-E1
R1
EE_SLC/EN
EE_SDA
Data Sheet
R2
½
102
103
+ 3 . 3 V
.
n c
8
6
5
U2
E E P R O M 2 4 C 0 4
VCC
SCL
SDA
G N D
TEST
A0
A1
A2
7
1
2
3
G N D
¼
½
March 2003 (rev. A)
) are done with the
). The CIP register
Cologne
Chip