HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 241

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_IRQ_MISC
Miscellaneous interrupt status register
All bits of this register are cleared after a read access.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
Name
V_STA_IRQ
V_TI_IRQ
V_IRQ_PROC
V_DTMF_IRQ
V_IRQ1S
V_SA6_IRQ
V_RX_EOMF
V_TX_EOMF
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
State change
’1’ = state of HFC-E1 interface state machine has
changed
Timer interrupt
’1’ = timer elapsed
Processing / non processing transition interrupt
status
’1’ = The HFC-E1 has changed from processing to
non processing phase (every 125 s).
DTMF detection interrupt
’1’ = DTMF detection has been finished. The
results can be read from the RAM.
1 second interrupt
’1’ = 1 second elapsed
SA6 pattern has changed or external interrupt
End of multiframe received
End of multiframe transmited
Cologne
Chip
241 of 272
0x11