HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 121

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_FIFO
FIFO selection register
This multi-register is selected with bitmap V_FSM_MD = 0 of the register
R_FIFO_MD. It is only used in SM and CSM.
0
5..1
6
7
R_FSM_IDX
Index register of the FIFO sequence
This multi-register is selected with bitmap V_FSM_MD = 1 of the register
R_FIFO_MD. It is only used in FSM.
5..0
7..6
Bits
Bits
0
0x00
0
0
Value
Value
Reset
Reset
V_FIFO_NUM
V_IDX
(reserved)
Name
V_FIFO_DIR
(reserved)
V_REV
Name
(write only)
(write only)
Data Sheet
Data flow
Description
FIFO data direction
’0’ = transmit FIFO data
’1’ = receive FIFO data
FIFO number
Must be ’0’.
Bit order
’0’ = normal bit order
’1’ = reversed bit order
Normal bit order means LSB first in HDLC mode
and MSB first in transparent mode. The bit order is
being reversed for the data stored into the FIFO or
when the data is read from the FIFO.
Description
List index
The list index must be in the range 0 . . . 63.
Must be ’00’.
Cologne
Chip
121 of 272
0x0F
0x0F