HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 63

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.5 Parallel processor interface
March 2003 (rev. A)
HFC-E1
Table 2.14: Overview of the parallel processor interface pins in mode 2 and 3
Table 2.15: Overview of the processor interface pins in mode 4
203 . . . 206, 1 . . . 4
6, 18, 30, 40
6, 18, 30, 40
Number
43 . . . 51
31 . . . 39
8 . . . 17
Number
43 . . . 51
31 . . . 39
Universal external bus interface
8 . . . 17
197
198
20
21
22
23
24
25
197
198
20
21
22
23
24
25
Name
A7 . . . A0
D7 . . . D0
D15 . . . D8
/BE3 . . . /BE0
/CS
/IOR
/IOW
/WD
ALE
/BUSDIR
/INT
RESET
Name
AD7 . . . AD0
AD15 . . . AD8
AD23 . . . AD16
AD31 . . . AD24
/BE3 . . . /BE0
/CS
/IOR
/IOW
/WD
ALE
/BUSDIR
/INT
RESET
Data Sheet
Description
Address byte
Data byte 0
Data byte 1
Byte Enable 3 . . . 0
Chip Select
Read Enable
Write Enable
Watch Dog Output
Address Latch Enable
Bus Direction
Interrupt request
Reset high active
Description
Address / Data byte 0
Address / Data byte 1
Address / Data byte 2
Address / Data byte 3
Byte Enable 3 . . . 0
Chip Select
Read Enable
Write Enable
Watch Dog Output
Address Latch Enable
Bus Direction
Interrupt request
Reset high active
Cologne
Chip
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