HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 246

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
246 of 272
R_IRQ_FIFO_BL3
FIFO interrupt register for FIFO block 3
In HDLC mode the end of frame is signaled, while in transparent mode the fre-
quency of interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If
a bit is ’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register
R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Reset
Value
Name
V_IRQ_FIFO12_TX
V_IRQ_FIFO12_RX
V_IRQ_FIFO13_TX
V_IRQ_FIFO13_RX
V_IRQ_FIFO14_TX
V_IRQ_FIFO14_RX
V_IRQ_FIFO15_TX
V_IRQ_FIFO15_RX
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Interrupt occured in transmit FIFO 12
Interrupt occured in transmit FIFO 13
Interrupt occured in transmit FIFO 14
Interrupt occured in transmit FIFO 15
Description
Interrupt occured in receive FIFO 12
Interrupt occured in receive FIFO 13
Interrupt occured in receive FIFO 14
Interrupt occured in receive FIFO 15
March 2003 (rev. A)
Cologne
Chip
0xCB