HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 67

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Address and /BE0 (if not fixed to low) require a setup time
and byte enable signals are valid. The hold time of these lines is
March 2003 (rev. A)
HFC-E1
G
In some applications it may be difficult to implement a long read access
(
For this reason there is an alternative method with two register read ac-
cesses with
The short read method is practical for all read registers in
the address range 0xC0 . . . 0xFF, these target registers are
R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 and R_RAM_DATA.
Ø
1. The read access to the target register initiates a data transmission
2. . . . but the data byte is already internally buffered and can be read
Short read method
from the RAM to the target register. This job is always done cor-
rectly with long and short
yet ‘arrived’ at the target register. Thus the data which is read with a
short
from the register R_INT_DATA. This second register read access
can also be executed with a short
the first access to the second one
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must be ignored . . .
) for only some registers (here called target register).
¾¼ Ò×
Universal external bus interface
each:
Data Sheet
Ø
, but after a short
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must be met, of course.
¾¼ Ò×
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Ë
. For the time from
which starts when all address
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À
the data is not
.
Cologne
Chip
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