IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 86

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–2
Figure 5–1. Signals in the Hard IP Implementation Root Port with Avalon-ST Interface Signals
Notes to
(1) Available in Arria GX, Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, Stratix II GX, and Stratix IV G devices. The reconfig_fromgxb is
(2) Available in Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, Stratix II GX, and Stratix IV GX, devices. For Stratix II GX and Arria GX
PCI Express Compiler User Guide
a single wire for Stratix II GX and Arria GX. For Stratix IV GX, <n> = 16 for ×1 and ×4 IP cores and <n> = 33 the ×8 IP core.
reconfig_togxb, <n> = 2. For Stratix IV GX, <n> = 3.
Reset &
Training
Link
Channell <n>)
Channel 0)
(Path to
Tx Port
Virtual
Figure
(Path to
Tx Port
Virtual
<variant>_plus
Reconfiguration
5–1:
Simulation
Clocks
Interrupt
Power
Mnmt
Completion
Interface
Component
Component
Avalon-ST
Reset
Avalon-ST
Clocks -
Only (2)
<variant>
Specific
(optional)
Specific
Completion
Interface
ECC Error
Component
Interrupts
Block
Clocks
Component
Avalon-ST
Power
Mnmt
Avalon-ST
Specific
Specific
rx_st_ready0
rx_st_valid0
rx_st_data0[63..0], [127:0]
rx_st_sop0
rx_st_eop0
rx_st_empty
rx_st_err0
rx_st_mask0
rx_st_bardec0[7:0]
rx_st_be0[7:0], [15:0]
rx_fifo_full0
rx_fifo_empty0
tx_st_ready0
tx_st_valid0
tx_st_data0[63..0], [127:0]
tx_st_sop0
tx_st_eop0
tx_st_empty
tx_st_err0
tx_fifo_full0
tx_fifo_empty0
tx_fifo_rdptr0[3:0]
tx_fifo_wrptr0[3:0]
tx_cred0[35..0]
refclk
pld_clk
core_clk_out
npor
srst
crst
l2_exit
hotrst_exit
dlup_exit
app_msi_req
app_msi_ack
app_msi_tc [2:0]
app_msi_num [4:0]
pex_msi_num [4:0]
app_int_sts
app_int_ack
pme_to_cr
pme_to_sr
cpl_err [6:0]
cpl_pending0
pclk_in
clk250_out
clk500_out
Signals in the PCI Express Hard IP MegaCore Function
pcie_rstn
local_rstn
suc_spd_neg
dl_ltssm[4:0]
npor
srst
crst
l2_exit
hotrst_exit
dlup_exit
reset_status
rc_pll_locked
tx_st_ready<n>
tx_st_valid<n>
tx_st_data<n>[63:0], [127:0]
tx_st_sop<n>
tx_st_eop<n>
tx_st_empty<n>
tx_st_err<n>
tx_fifo_full<n>
tx_fifo_empty<n>
tx_fifo_rdptr<n>[3:0]
tx_fifo_wrptr<n>[3:0]
tx_cred<n>[35:0]
nph_alloc_1cred_vc0
npd_alloc_1cred_vc0
npd_cred_vio_vc0
nph_cred_vio_vc0
refclk
pld_clk
core_clk_out
avs_pcie_reconfig_address[7:0]
avs_pcie_reconfig_byteenable[1:0]
avs_pcie_reconfig_chipselect
avs_pcie_reconfig_write
avs_pcie_reconfig_writedata[15:0]
avs_pcie_reconfig_waitrequest
avs_pcie_reconfig_read
avs_pcie_reconfig_readdata[15:0]
avs_pcie_reconfig_readdatavalid
avs_pcie_reconfig_clk
avs_pcie_reconfig_rstn
pme_to_cr
pme_to_sr
pm_data
pm_auxpwr
derr_cor_ext_rcv[1:0]
derr_rpl
derr_cor_ext_rpl
r2c_err0
r2c_err1
aer_msi_num[4:0]
pex_msi_num[4:0]
int_status[4:0]
serr_out
rx_st_ready<n>
rx_st_valid<n>
rx_st_data<n>[63:0], [127:0]
rx_st_sop<n>
rx_st_eop<n>
rx_st_empty<n>
rx_st_err<n>
rx_st_mask<n>
rx_st_bardec<n>[7:0]
rx_st_be<n>[7:0], [15:0]
cpl_err[6:0]
cpl_pending<n>
Signals in the PCI Express Hard IP Core
(1)
(1)
(1)
reset_reconfig_altgxb_reconfig
busy_reconfig_altgxb_reconfig
reconfig_fromgxb[1:0]
powerdown0_ext[1:0]
(1)
reconfig_togxb[2:0]
reconfig_fromgxb[<n>:0]
(2)
rxstatus0_ext[2:0]
txdata0_ext[7:0]
rxdata0_ext[7:0]
tl_cfg_sts[52:0]
tl_cfg_add[3:0]
reconfig_togxb[<n>:0]
powerdown0_ext[1:0]
txdetectrx0_ext
phystatus0_ext
rxelecidle0_ext
tl_cfg_ctl[31:0]
txelecidle0_ext
rxpolarity0_ext
rx_st_fifo_empty<n>
test_out[64:0]
lmi_dout[31:0]
lmi_addr[11:0]
tl_cfg_sts_wr
txcompl0_ext
tl_cfg_ctl_wr
rxdatak0_ext
txdatak0_ext
test_in[15:0]
lmi_din[31:0]
rxvalid0_ext
reconfig_clk
rxstatus0_ext[2:0]
pipe_mode
cal_blk_clk
rx_st_fifo_full<n>
gxb_powerdown
rxdata0_ext[7:0]
txdata0_ext[7:0]
tx_pipedeemph
tl_cfg_sts[52:0]
txdetectrx0_ext
lmi_wren
phystatus0_ext
rxelecidle0_ext
tl_cfg_add[3:0]
lmi_rden
txelecidle0_ext
tl_cfg_ctl[31:0]
rxpolarity0_ext
rate_ext
hpg_ctrler[4:0]
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
tx_pipemargin
lmi_ack
test_out[63:0]
lmi_dout[31:0]
lmi_addr[11:0]
tl_cfg_sts_wr
txcompl0_ext
lane_act[3:0]
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
txdatak0_ext
rxdatak0_ext
tl_cfg_ctl_wr
reconfig_clk
lmi_din[31:0]
test_in[39:0]
rxvalid0_ext
cal_blk_clk
pipe_mode
clk250_out
clk500_out
pipe_txclk
pipe_rstn
lmi_wren
lmi_rden
rate_ext
fixedclk
lmi_ack
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
pclk_in
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
December 2010 Altera Corporation
8-bit
PIPE
Transceiver
internal
Serial
Config
Control
PHY
IF to
PIPE
LMI
Test
Interface
for
Chapter 5: IP Core Interfaces
Repeated for
Lanes 1-7
<variant>_plus.v or .vhd)
8-bit
PIPE
Simulation
Test
Interface
Config
internal
Clocks -
Serial
LMI
PHY
IF to
PIPE
Only
These signals are
for
Transceiver
internal for
Control
Avalon-ST Interface
Simulation
Simulation
Interface
Interface
Only (2)
PIPE
Only
PIPE