IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet

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... PCI Express Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-PCI10605-2.8 PCI Express Compiler User Guide ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Avalon-ST Application Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 RX Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 TX Datapath—Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, and Stratix 4–6 LMI Interface (Hard IP Only 4–7 PCI Express Reconfiguration Block Interface (Hard IP Only 4–7 MSI (Message Signal Interrupt) Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– ...

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... ECC Error Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 PCI Express Interrupts for Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 PCI Express Interrupts for Root Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 Configuration Space Signals—Hard IP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix 5–32 Stratix V Hard IP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35 Configuration Space Register Access Timing - Stratix 5–37 Configuration Space Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5– ...

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... Avalon-ST Interface—Soft IP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 Clocking for a Generic PIPE PHY and the Simulation Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 100 MHz Reference Clock and 125 MHz Application Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 100 MHz Reference Clock and 250 MHz Application Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Clocking for a Generic PIPE PHY and the Simulation Testbench . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Avalon-MM Interface– ...

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... Root Port Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–4 Chaining DMA Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–6 Design Example BAR/Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–13 Chaining DMA Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–14 Chaining DMA Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–17 Test Driver Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–18 DMA Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–19 DMA Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–21 Root Port Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–22 Root Port BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15– ...

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... Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–51 dma_wr_test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_rd_desc_data Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_wr_desc_data Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 dma_set_header Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–52 rc_mempoll Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–53 msi_poll Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–53 dma_set_msi Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–54 find_mem_bar Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–54 dma_set_rclast Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–55 ebfm_display_verb Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–55 December 2010 Altera Corporation vii PCI Express Compiler User Guide ...

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... Transmit Operation Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–12 Transmit Datapath Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–12 Transaction Examples Using Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–17 Completion Interface Signals for Descriptor/Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–25 Incremental Compile Module for Descriptor/Data Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–26 ICM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–27 ICM Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–27 <variation_name>_icm Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–28 ICM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–29 ICM Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B– ...

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... Contents Stratix IV Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–6 Descriptor/Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–6 Arria GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–7 Cyclone III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–7 Stratix II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–8 Stratix III Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–8 Stratix IV Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–9 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–8 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–8 December 2010 Altera Corporation ...

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... PCI Express Compiler User Guide Contents December 2010 Altera Corporation ...

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... Table 1–1 shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 PCI Express IP cores for and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5 giga-transfers per second for Gen2. Because the PCI Express protocol uses 8B10B encoding, there is a 20% overhead which is included in ...

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... Extensive maximum payload size support: ■ Stratix IV GX and Stratix V GX hard IP— KBytes (128, 256, 512, 1,024, or 2,048 bytes). Arria II GX and Cyclone IV GX hard IP—Up to 256 bytes (128 or 256). Soft IP Implementations— KBytes (128, 256, 512, 1,024, or 2,048 bytes). ...

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... Chapter 1: Datasheet Features Different features are available for the soft and hard IP implementations and for the three possible design flows. Table 1–2. PCI Express IP core Features (Part Feature MegaCore License Root port Gen1 Gen2 Avalon Memory-Mapped (Avalon-MM) Interface 64-bit Avalon Streaming ...

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... DesignFlow Flow 4–256 16 Not supported Not supported Not supported Not supported Not supported Not supported Description 10.1 December 2010 IP-PCIE/1 IP-PCIE/4 IP-PCIE/8 IP-AGX-PCIE/1 IP-AGX-PCIE/4 FFFF ×1–00A9 ×4–00AA ×8–00AB 6AF7 6A66 ® II software compiles the December 2010 Altera Corporation ...

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... Note to Table 1–4: (1) To successfully compile your IP core using the Quartus II software, you must install support for the Stratix II GX family even if you have selected the Arria GX or Arria II GX device family. General Description The PCI Express Compiler generates customized PCI Express IP cores you use to ...

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... The hard IP implementation includes all of the required and most of the optional features of the specification for the transaction, data link, and physical layers. Depending upon the device you choose, one to four instances of the hard PCI Express IP core are available. These instances can be configured to include any combination of root port and endpoint designs to meet your system requirements ...

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... Program Object File (.pof) programmed the I/O ring and FPGA fabric before the PCIe link training and enumeration began. In Stratix V, the .pof file is divided into two parts. The IO bitstream contains the data to program the I/O ring and PCI Express IP core. The core bitstream contains the data to program the FPGA fabric. ...

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... IP cores to meet your design requirements.Table 1–5 hard IP implementation. Table 1–5. PCIe Hard IP Configurations for the PCIe Compiler in the Quartus II Software in Version 10.1 (Part Device Link Rate (Gbps) Avalon Streaming (Avalon-ST) Interface using MegaWizard Plug-In Manager Design Flow 2 ...

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... Chapter 1: Datasheet General Description Table 1–5. PCIe Hard IP Configurations for the PCIe Compiler in the Quartus II Software in Version 10.1 (Part Device Link Rate (Gbps) 2.5 Cyclone IV GX 5.0 2.5 Stratix IV GX 5.0 Note to Table 1–5: (1) For devices that do not offer a ×2 initial configuration, you can use a ×4 configuration with the upper two lanes left unconnected at the device pins. The link will negotiate to × ...

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... Figure 1–4 illustrates a heterogeneous topology, including an Altera device with two PCIe hard IP root ports. One root port connects directly to a second FPGA that includes an endpoint implemented using the hard IP IP core. The second root port connects to a switch that multiplexes among three PCI Express endpoints. ...

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... External PHY Support Altera PCI Express IP cores support a wide range of PHYs, including the TI XIO1100 PHY in 8-bit DDR/SDR mode or 16-bit SDR mode; NXP PX1011A for 8-bit SDR mode, a serial PHY, and a range of custom PHYs using 8-bit/16-bit SDR with or without source synchronous transmit clock modes and 8-bit DDR with or without source synchronous transmit clock modes ...

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... All PCI-SIG compliance tests are also run with each IP core release. Performance and Resource Utilization The hard IP implementation of the PCI Express IP core is available in Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix IV GX, and Stratix V devices. PCI Express Compiler User Guide ...

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... For soft IP implementations of the PCI Express IP core, the table lists speed grades that are likely to meet timing; it may be possible to close timing in a slower speed grade. For the hard IP implementation, the speed grades listed are the only speed grades that close timing ...

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... Arria II GX Cyclone II, Cyclone III Cyclone IV GX Gen1 with ECC Support Stratix II PCI Express Compiler User Guide in volume 2 of the Quartus II Handbook for more Internal Clock Link Width Frequency (MHz) Avalon-ST Hard IP Implementation ×1 62.5 ×1 125 (1) ×4 125 ×8 125 × ...

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... Explorer or Quartus II seed sweeping methodology. Refer to the chapter in volume 1 of the Quartus II Development Software Handbook for more information about how to set these options. (8) Altera recommends disabling the OpenCore Plus feature for the ×8 soft IP implementation because including this feature makes it more difficult to close timing. OpenCore Plus Evaluation You can use Altera's free OpenCore Plus evaluation feature to evaluate the IP core in simulation and in hardware before you purchase a license ...

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... After you purchase a license for the PCI Express IP core, you can request a license file from the Altera licensing website at (www.altera.com/licensing) and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have internet access, contact your local Altera representative. ...

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... Specify a variation name for output files <working_dir>\<variation name>. For this walkthrough, specify top.v for the name of the IP core files: <working_dir>\top.v. 7. Click Next to display the Parameter Settings page for the PCI Express IP core. 1 You can change the page that the MegaWizard Plug-In Manager displays by clicking Next or Back at the bottom of the dialog box ...

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... Max rate Test out width PCIe reconfig PCI Express Compiler User Guide specifies the parameters to run the testbench. provides the correct System Settings. Parameter PCI Express hard IP Stratix IV GX serial Use default settings. ×8 100 MHz Avalon-ST 128 -bit Native Endpoint 2 ...

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... Table 2–2. PCI Registers (Part PCI Base Registers (Type 0 Configuration Space) BAR Register Name Device ID Subsystem ID Revision ID December 2010 Altera Corporation Figure 2–2. Bar2 or Bar3 is required. BAR TYPE 32-Bit Non-Prefetchable Memory 32-Bit Non-Prefetchable Memory 32-bit Non-Prefetchable Memory PCI Read-Only Registers Value 0xE001 ...

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... ABCD Error Reporting Off Off Off Off MSI Capabilities 4 On Link Capabilities On Off Off 0x01 Slot Capabilities Off 0x0000000 MSI-X Capabilities Off 0x000 0x00000000 0 0x00000000 0 Chapter 2: Getting Started Parameterize the PCI Express provides the correct settings Value December 2010 Altera Corporation ...

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... Desired performance for received requests Desired performance for received completions 1 For the PCI Express hard IP implementation, the RX Buffer Space Allocation is fixed at Maximum performance. This setting determines the values for a read-only table that lists the number of posted header credits, posted data credits, non-posted header credits, completion header credits, completion data credits, total header credits, and total RX buffer space ...

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... A report file, <variation name>.html, in your project directory lists each file generated and provides a description of its contents. 18. Click Yes when you are prompted to add the Quartus II IP File (.qip) to the project. The .qip is a file generated by the parameter editor or SOPC Builder that contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler ...

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... The simulation files for the chaining DMA design example, stored in the <working_dir>\top_examples\chaining_dma\testbench sub-directory. The Quartus II software generates the testbench files if you turn on Generate simulation model on the EDA tab while generating the PCIe IP core. 0 Figure 2–4. Directory Structure for PCI Express IP Core and Testbench ...

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... Stratix IV GX files. You also must also download altpcie_demo.zip which includes a software driver that the example design uses. The Stratix IV .zip file includes files for Gen1 and Gen2 ×1, ×4, and ×8 variants. The example in this document demonstrates the Gen2 ×8 variant. After you download and unzip this .zip file, you can copy the files for this variant to your project directory, < ...

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... RP LTSSM State: CONFIG.IDLE # INFO: 11356 ns RP LTSSM State INFO: 11580 ns EP LTSSM State: L0 December 2010 Altera Corporation illustrates, the scripts to run the simulation files are located in the shows the a partial transcript from a successful simulation. As this 2–9 ® software. PCI Express Compiler User Guide ...

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... EP LTSSM State INFO: 23152 ns Current Link Speed: 5.0GT/s # INFO: 27936 ns --------- # INFO: 27936 ns TASK:dma_set_header READ # INFO: 27936 ns Writing Descriptor header # INFO: 27976 ns data content of the DT header # INFO: 27976 ns # INFO: 27976 ns Shared Memory Data Display: # INFO: 27976 ns Address Data # INFO: 27976 ns ------- ---- ...

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... INFO: 27936 ns msi_number = 0000 # INFO: 27936 ns msi_traffic_class = 0000 # INFO: 32976 ns TASK:dma_set_header WRITE # INFO: 32976 ns Writing Descriptor header # INFO: 33016 ns data content of the DT header # INFO: 33016 ns # INFO: 33016 ns Shared Memory Data Display: # INFO: 33016 ns Address Data # INFO: 33016 ns ------- ---- ...

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... Before compiling the design using the Quartus II software, you must apply appropriate design constraints, such as timing constraints. The Quartus II software automatically generates the constraint files when you generate the PCI Express IP core. Table 2–6 describes these constraint files. Table 2–6. Automatically Generated Constraints Files ...

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... MHz" -name {refclk} {refclk} set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}] set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }] <The following 4 additional constraints are for Stratix IV ES Silicon only> set_multicycle_path -from [get_registers *delay_reg*] -to [get_registers *all_one*] - hold -start 1 ...

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... IO_STANDARD "2.5 V" -to lane_active_led[2] set_instance_assignment -name IO_STANDARD "2.5 V" -to lane_active_led[3] set_instance_assignment -name IO_STANDARD "2.5 V" -to L0_led set_instance_assignment -name IO_STANDARD "2.5 V" -to alive_led set_instance_assignment -name IO_STANDARD "2.5 V" -to comp_led PCI Express Compiler User Guide Chapter 2: Getting Started Constrain the Design December 2010 Altera Corporation ...

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... This optimization performs automatic pipelining of these signals, while attempting to minimize the total number of registers inserted. Compile for the Design To test your PCI Express IP core in hardware, your initial Quartus II compilation includes all of the directories shown in customized design, you can exclude the testbench directory from the Quartus II compilation ...

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... PCI Express Compiler User Guide Chapter 2: Getting Started Reusing the Example Design December 2010 Altera Corporation ...

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... PCIe System Parameters Allows all types of external PHY interfaces (except serial). The number of lanes can be ×1 or ×4. This option is only available for the soft IP implementation. Serial interface where Stratix II GX uses the Stratix II GX device family's built-in transceiver. Selecting this PHY allows only a serial PHY interface with the lane configuration set to Gen1 × ...

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... Settings for PCI Express (PIPE)” in the Setup Guide for an explanation of these settings. You do not need to change any of the PIPE PHY for Stratix V GX transceiver. To learn more about this IP core, refer to the “PCI Express PIPE PHY IP User Guide “ in the Altera Transceiver PHY IP Core User Guide ...

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... MHz or 125 MHz reference clock for Gen1 operation; Gen2 requires a 100 MHz clock. The Arria GX and Stratix II GX devices require a 100 MHz clock. If you use a PIPE interface (and the PHY type is not Arria GX, Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix II GX, or Stratix IV GX) the refclk is not required ...

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... Quartus II compilation. PCI Registers The ×1 and ×4 IP cores support memory space BARs ranging in size from 128 bytes to the maximum allowed by a 32-bit or 64-bit BAR. The ×8 IP cores support memory space BARs from 4 KBytes to the maximum allowed by a 32-bit or 64-bit BAR. ...

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... Vendor ID 0x1172 0x000 December 2010 Altera Corporation Description BAR0 size and type mapping (I/O space (1), memory space). BAR0 and BAR1 can be combined to form a 64-bit prefetchable BAR. BAR0 and BAR1 can be configured separate as 32-bit non-prefetchable memories.) (2) BAR1 size and type mapping (I/O space (1), memory space. BAR0 and BAR1 can be combined to form a 64-bit prefetchable BAR ...

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... Only available for RP designs which require the use of the Header type 1 PCI configuration register. Capabilities Parameters The Capabilities page contains the parameters setting various capability properties of the IP core. These parameters are described in stored in the Common Configuration Space Common Configuration Space Header PCI Express Compiler User Guide Sets the read-only value of the subsystem vendor ID register ...

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... The following options are available: Hard IP tags for ×1, ×4, and ×8 Soft IP: 4–256 tags for ×1 and ×4; 4–32 for ×8 SOPC Builder: 16 tags for ×1 and ×4 This parameter sets the values in the Device Control register (0x088) of the PCI ...

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... This parameter requires you to implement the advanced error reporting capability. Available for hard IP implementation only. Forward ECRC to the application layer. On the Avalon-ST receive path, the incoming TLP contains the ECRC dword and the TD bit is set if an ECRC exists ...

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... Power Controller Present Attention Button Present MSI-X Capabilities (0x68, 0x6C, 0x70) The MSI-X functionality is only available in the hard IP implementation. System software reads this field to determine the MSI-X Table size <N>, which is encoded as <N–1>. For example, a returned value of 10’b00000000011 indicates a table size of 4 ...

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... Sets the size of the retry buffer for storing transmitted PCI Express packets until acknowledged. This option is only available if you do not turn on Auto configure retry buffer size. The hard IP retry buffer is fixed at 4 KBytes for Arria II GX and Cyclone IV GX devices KBytes for Stratix IV GX devices, and at 8 KBytes for Stratix V GX devices ...

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... This setting minimizes the device resource utilization. Because the Arria II GX and Stratix IV hard IP have a fixed RX Buffer size, the choices for this parameter are limited to a subset of these values. For Max payload size of 512 bytes or less, the only available value is Maximum ...

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... PCI Express link as is required for endpoints the application layer to manage the rate of non-posted requests to ensure that the RX buffer completion space does not overflow. The hard IP RX buffer is fixed at 16 KBytes for Stratix IV GX devices and 4 KBytes for Arria II GX devices. ...

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... Arria GX, Arria II GX, Cyclone IV GX, Stratix II GX, Stratix Stratix V GX PHY, this parameter is disabled and set to its maximum value. If you are using an external PHY, consult the PHY vendor's documentation to determine the correct value for this parameter. Description PCI Express Compiler User Guide 3–13 ...

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... PCI Express Compiler User Guide Description Allows you to specify one or two clock domains for your application and the PCI Express IP core. The single clock domain is higher performance because it avoids the clock crossing logic that separate clock domains require. Use PCIe core clock—In this mode, the PCI Express IP core provides a clock output, clk125_out used as the single clock for the PCI Express IP core and the SOPC Builder system ...

Page 57

... Enable Avalon-MM CRA port Disable December 2010 Altera Corporation Description Sets Avalon-MM-to-PCI Express address translation windows and size. Specifies the number of PCI Express base address pages of memory that the bridge can access. This value corresponds to the number of entries in the address translation table. The Avalon address range is segmented into one or more equal-sized pages that are individually mapped to PCI Express addresses ...

Page 58

... PCI Express Compiler User Guide Chapter 3: Parameter Settings Avalon-MM Configuration December 2010 Altera Corporation ...

Page 59

... December 2010 <edit Part Number variable in chapter> This chapter describes the architecture of the PCI Express Compiler. For the hard IP implementation, you can design an endpoint using the Avalon-ST interface or Avalon-MM interface root port using the Avalon-ST interface. For the soft IP implementation, you can design an endpoint using the Avalon-ST, Avalon-MM or Descriptor/Data interface ...

Page 60

... PCI Express IP Core Tx Port Avalon-ST Interface or Avalon-MM Interface Rx Port or Data/Descriptor Interface Application Interfaces This chapter provides an overview of the architecture of the Altera PCI Express IP core. It includes the following sections: Application Interfaces ■ ■ Transaction Layer ■ Data Link Layer ■ Physical Layer PCI Express Avalon-MM Bridge ■ ...

Page 61

... Stratix V devices do not require the adapter module. Figure 4–3 and Express IP core. In both cases the adapter maps the user application Avalon-ST interface to PCI Express TLPs. The hard IP and soft IP implementations differ in the following respects: ■ The hard IP implementation includes dedicated clock domain crossing logic between the PHYMAC and data link layers ...

Page 62

... Figure 4–3. PCI Express Hard IP Implementation with Avalon-ST Interface to User Application PCI Express Hard IP Core PIPE Transceiver PHYMAC Figure 4–4. PCI Express Soft IP Implementation with Avalon-ST Interface to User Application PCI Express Soft IP Core PIPE Transceiver PHYMAC PCI Express Compiler User Guide Clock & ...

Page 63

... Table 4–1 provides the application clock frequencies for the hard IP and soft IP implementations. As this table indicates, the Avalon-ST interface can be either 64 or 128 bits for the hard IP implementation. For the soft IP implementation, the Avalon-ST interface is 64 bits. Table 4–1. Application Clock Frequencies Lanes × ...

Page 64

... Avalon-ST adapter. For example, if the tx_cred value is 5, the application layer has 5 credits available to it. For completions and posted requests, the tx_cred vector reflects the credits available in the transaction layer of the PCI Express IP core. For example, for completions and posted requests, if tx_cred is 5, the actual credits available to the application is (5 – ...

Page 65

... When the TX block application drives a packet to the Avalon-ST adapter, the packet remains in the TX datapath FIFO as long as the IP core throttles this interface. When it is necessary to send an MSI request after a specific TX packet, you can use the TX FIFO empty flag to determine when the IP core receives the TX packet. December 2010 Altera Corporation “ ...

Page 66

... Stratix IV GX Devices To Application Incremental Compilation The IP core with Avalon-ST interface includes a fully registered interface between the user application and the PCI Express transaction layer. For the soft IP implementation, you can use incremental compilation to lock down the placement and routing of the PCI Express IP core with the Avalon-ST interface to preserve placement and timing while changes are made to your application ...

Page 67

... You can parameterize the Stratix core to include one or two virtual channels. The Arria II GX, Cyclone IV GX, and Stratix V GX implementations include a single virtual channel. Tracing a transaction through the receive datapath includes the following steps: 1 ...

Page 68

... Packet FIFO Flow Control Update Receive Buffer Tx Flow Control Credits Posted & Completion Non-Posted Transaction Layer Packet FIFO Rx Transaction Flow Control Update Layer Packet Chapter 4: IP Core Architecture Transaction Layer Transmit Data Path Configuration Space Receive Data Path December 2010 Altera Corporation ...

Page 69

... Transmit Virtual Channel Arbitration For Stratix IV GX devices, the PCI Express IP core allows you to specify a high and low priority virtual channel as specified in Chapter 6 of the Specification 1.0a, 1.1 or accessible from the Parameter Settings tab, to specify the number of virtual channels ...

Page 70

... The data link layer has the following subblocks: PCI Express Compiler User Guide DLLP Tx Arbitration Generator Ack/Nack Packets Power Management Function DLLP Checker Chapter 4: IP Core Architecture Data Link Layer To Physical Layer Tx Packets Transmit Data Path Control Data Link Control & Status & Management State Machine Receive ...

Page 71

... ACK/NAK FC data link layer packet (low priority) Physical Layer The physical layer is the lowest level of the IP core the layer closest to the link. It encodes and transmits packets across a link and accepts and decodes received packets. The physical layer connects to the link through a high-speed SERDES interface running at 2 ...

Page 72

... Lane n Descrambler Rx Packets Lane 0 Descrambler The physical layer is subdivided by the PIPE Interface Specification into two layers (bracketed horizontally in ■ Media Access Controller (MAC) Layer—The MAC layer includes the Link Training and Status state machine (LTSSM) and the scrambling/descrambling and multilane deskew functions. ...

Page 73

... Physical Layer The physical layer integrates both digital and analog elements. Intel designed the PIPE interface to separate the MAC from the PHY. The IP core is compliant with the PIPE interface, allowing integration with other PIPE-compliant external PHY devices. Depending on the parameters you set in the parameter editor, the IP core can automatically instantiate a complete PHY layer when targeting the Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix II GX, Stratix Stratix V GX devices ...

Page 74

... RX Master Module—This 64-bit bursting Avalon-MM master port propagates PCI Express requests, converting them to bursting read or write requests to the system interconnect fabric. PCI Express Compiler User Guide Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge Figure 4–10, provides December 2010 Altera Corporation ...

Page 75

... Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge ■ Control Register Access (CRA) Slave Module—This optional, 32-bit Avalon-MM dynamic addressing slave port provides access to internal control and status registers from upstream PCI Express devices and external Avalon-MM masters. Implementations that use MSI or dynamic address translation require this port. ...

Page 76

... The Avalon-MM byte enable must be asserted in the first qword of the burst. ■ All subsequent byte enables must be asserted until the deasserting byte enable. ■ PCI Express Compiler User Guide Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge December 2010 Altera Corporation ...

Page 77

... The address translation lookup table values are user configurable. Unsupported read requests generate a completer abort response. 1 PCIe IP cores using the Avalon-ST interface can handle burst reads up to the specified Maximum Payload Size. December 2010 Altera Corporation 4–19 ...

Page 78

... Avalon-MM slave to PCI Express completion packets and sends them to the transaction layer. A single read request may produce multiple completion packets based on the Maximum Payload Size and the size of the received read request. For example, if the read is 512 bytes but the Maximum Payload Size 128 bytes, the bridge produces four completion packets of 128 bytes each ...

Page 79

... Avalon-MM address with the value from a specific translation table entry; the LSB bits remain unchanged. The number of MSB bits to be replaced is calculated based on the total address space of the upstream PCI Express devices that the PCI Express IP core can access. December 2010 Altera Corporation depicts the PCI Express Avalon-MM bridge address ...

Page 80

... Bits [19:0] are passed through and become PCI Express address bits [19:0]. The address translation table can be hardwired or dynamically configured at run time. When the IP core is parameterized for dynamic address translation, the address translation table is implemented in memory and can be accessed through the CRA slave module ...

Page 81

... Address: 0x3060”. For interrupts due to the RXmIrq_i signal, the interrupt status should be cleared in the other Avalon peripheral that sourced the interrupt. This sequence prevents interrupts from being lost during interrupt servicing. December 2010 Altera Corporation (Note 1) (2) (3) (4) (5) ...

Page 82

... DEASSERT_INTA Message Sent) SET CLR MSI Enable (Table 11–1) can be used to disable legacy interrupts. The MSI enable 11–5, can be used to enable MSI interrupts. Only one type of Chapter 4: IP Core Architecture PCI Express Avalon-MM Bridge MSI Request “PCI and December 2010 Altera Corporation ...

Page 83

... As this figure illustrates, the PCI Express IP core links to a PCI Express root complex. A bridge component includes PCIe TX and RX blocks, a PCIe RX master, and an interrupt handler. It connects to the FPGA fabric using an Avalon-MM interface. The following sections provide an overview of each of block in the bridge. ...

Page 84

... PCI Express IP core are not accepted while a request is being processed. For reads, the RX block deasserts the ready signal until the corresponding completion packet is sent to the PCI Express IP core via the PCIe TX block. For writes, requests must be sent to the Avalon-MM system interconnect fabric before the next request is accepted. ...

Page 85

... December 2010 <edit Part Number variable in chapter> This chapter describes the signals that are part of the PCI Express IP core for each of the following primary configurations: Signals in the Hard IP Implementation Root Port with Avalon-ST Interface Signals ■ ■ Signals in the Hard IP Implementation Endpoint with Avalon-ST Interface ■ ...

Page 86

... Available in Arria GX, Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, Stratix II GX, and Stratix IV G devices. The reconfig_fromgxb is a single wire for Stratix II GX and Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, Stratix II GX, and Stratix IV GX, devices. For Stratix II GX and Arria GX reconfig_togxb, < ...

Page 87

... Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> For Stratix IV GX, < ...

Page 88

... Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> For Stratix IV GX, < ...

Page 89

... Chapter 5: IP Core Interfaces Avalon-ST Interface Figure 5–4. Signals in the Hard IP Implementation with Avalon-ST Interface for Stratix V Devices Avalon-ST Component Specific Avalon-ST Tx Port Component Specific Clocks <variant>_plus Reset & Link <variant> Training Reconfiguration Block (optional) ECC Error Interrupts (Root Port) Completion ...

Page 90

... Table 5–1 lists the interfaces of both the hard IP and soft IP implementations with links to the subsequent sections that describe each interface. Table 5–1. Signal Groups in the PCI Express IP core with Avalon-ST Interface Hard IP Signal Group End Root point Port v v Avalon-ST RX ...

Page 91

... TLP payload, the packet may be terminated early error with an rx_st_eop and with rx_st_valid deasserted on the cycle after the eop. This signal is only active for the hard IP implementations when ECC is enabled. This signal is not available for the hard IP implementation in Arria II GX devices ...

Page 92

... In Stratix IV GX devices, <n> is the virtual channel number, which can (2) The RX interface supports a readyLatency of 2 cycles for the hard IP implementation and 3 cycles for the soft IP implementation. To facilitate the interface to 64-bit memories, the IP core always aligns data to the qword or 64 bits; consequently, if the header presents an address that is not qword aligned, the IP core, shifts the data within the qword to achieve the correct alignment. Figure 5– ...

Page 93

... Chapter 5: IP Core Interfaces Avalon-ST Interface writes, configuration writes, and I/O writes. The alignment of the request TLP depends on bit 2 of the request address. For completion TLPs with data, alignment depends on bit 2 of the lower address field. This bit is always 0 (aligned to qword boundary) for completion with data TLPs that are for configuration read or I/O read requests ...

Page 94

... Note that the Avalon-ST protocol, as defined in endian, while the PCI Express IP core packs symbols into words in little endian format. Consequently, you cannot use the standard data format adapters available in SOPC Builder with PCI Express IP cores that use the Avalon-ST interface. ...

Page 95

... Chapter 5: IP Core Interfaces Avalon-ST Interface Figure 5–9 shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs for a four dword header with non-qword addresses with a 64-bit bus. Note that the address of the first dword is 0x4. The address of the first enabled byte is 0x6. This example shows one valid word in the first dword, as indicated by the rx_st_be signal. Figure 5– ...

Page 96

... Header 0 Data 1 Data (n-1) Header 3 Data 2 Header 2 Data 1 Data n Header 1 Data 0 Data n-1 Header 0 Data n-2 Header3 Data3 Data n Header 2 Data 2 Data n-1 Header 1 Data 1 Data n-2 Header 0 Data 0 Data n-3 Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 97

... Chapter 5: IP Core Interfaces Avalon-ST Interface f For a complete description of the TLP packet header formats, refer to Transaction Layer Packet (TLP) Header Figure 5–14 illustrates the timing of the Avalon-ST RX interface. On this interface, the core deasserts rx_st_valid in response to the deassertion of rx_st_ready from the application. ...

Page 98

... Avalon-ST Type implementation. When tx_st_ready<n> reasserts, and tx_st_data<n> mid-TLP, this signal must reassert within 3 cycles for soft IP and 2 cycles for the hard IP implementation. Refer to the timing of this signal. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid ...

Page 99

... O consumed than the tx_cred signal advertised. Once a specific violation is detected, this signal remains high until the IP core is reset. Used in conjunction with the optional tx_cred<n> signal. When 1, means that the non-posted header credit field is no longer valid. This indicates that more credits ...

Page 100

... PCI Express Compiler User Guide Avalon-ST Type Component Specific Signals for Stratix V Asserted for 1 cycle each time the IP core consumes a credit. The 6 bits of this vector correspond to the following 6 types of credit types: [5]–posted headers ■ [4]–posted data ■ component [3]– ...

Page 101

... For all signals, <n> is the virtual channel number, which can ( Avalon-ST compliant, you must use a readyLatency for hard IP implementation, and a readyLatency for the soft IP implementation. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals other delays are added to the ready-valid latency, this corresponds to a readyLatency of 2. ...

Page 102

... Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} (6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} PCI Express Compiler User Guide illustrates the storage of non-qword aligned data.) 2 Header1 Data0 Header0 Header2 2 Header1 Header3 Header0 Header2 Chapter 5: IP Core Interfaces Avalon-ST Interface 3 Data2 Data1 3 Data1 Data0 December 2010 Altera Corporation ...

Page 103

... Chapter 5: IP Core Interfaces Avalon-ST Interface Figure 5–18 illustrates the mapping between Avalon-ST TX packets and PCI Express TLPs for four dword header with non-qword aligned addresses with a 64-bit bus. Figure 5–18. 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-DWord Header with Non-QWord Aligned Address ...

Page 104

... PCI Express Compiler User Guide Header 3 Data 3 Header 2 Data 2 Header 1 Data 1 Header 0 Data 0 Data 4 Header 3 Data 2 Data n Header 2 Data 1 Data n-1 Header 1 Data 0 Data n-2 Header 0 Chapter 5: IP Core Interfaces Avalon-ST Interface December 2010 Altera Corporation ...

Page 105

... Chapter 5: IP Core Interfaces Avalon-ST Interface Figure 5–23 illustrates the layout of header and data for a 3-DWord header for 256-bit with aligned and unaligned data. Figure 5–23. 256-Bit Avalon-ST tx_sd_data Cycle Definition for 3-DWord Header TLP with QWord Aligned Address clk tx_st_data[63:0] ...

Page 106

... Notes to Figure 5–25: (1) The maximum allowed response time is 3 clock cycles for the soft IP implementation and 2 clock cycles for the hard IP implementation. Root Port Mode Configuration Requests To ensure proper operation when sending CFG0 transactions in root port mode, the application should wait for the CFG0 to be transferred to the IP core’s configuration space before issuing another packet on the Avalon-ST TX port ...

Page 107

... This is a fixed frequency clock used by the data link and transaction layers. To meet PCI O Express link bandwidth constraints, it has minimum frequency requirements which are core_clk_out outlined in This is used for simulation only, and is derived from the refclk the PIPE interface clock p_clk I used for PIPE mode simulation. O This is used for simulation only ...

Page 108

... L2 low power mode or upon a fundamental pcie_rstn reset. This is an asynchronous reset. This signal is not used in Stratix V devices. reset_n is the system-wide reset which resets all PCI Express IP core circuitry not affected by I local_rstn pcie_rstn. This is an asynchronous reset.This signal is not used in Stratix V devices. ...

Page 109

... Stratix V devices. Synchronous datapath reset. This signal is the synchronous reset of the datapath state I machines of the IP core active high. This signal is only available on the hard IP and soft IP srst ×1 and ×4 implementations. This signal is not used for Stratix V devices. ...

Page 110

... Table 5–7. Reset and Link Training Signals (Part Signal I/O This signal is active for one pld_clk cycle when the IP core exits the DLCSM DLUP state. In endpoints, this signal should cause the application to assert a global reset (crst and srst in O the hard IP implementation and ×1 and ×4 soft IP implementation, or rstn in ×8 the soft IP dlup_exit implementation) ...

Page 111

... The PCI Express IP core soft IP implementation (×8) has two reset inputs, npor and rstn. The npor reset is used internally for all sticky registers that may not be reset in L2 low power mode or by the fundamental reset ...

Page 112

... Initialize the I/O ring and PCI Express hard IP core. 2. Initialize the PCI Express link. 3. Configure the FPGA fabric which can be performed using CvPCIe. 4. After the PLD clock is ready, the PCI Express IP core asserts pld_clk_in_use to indicate that it is operating in user mode. Figure 5–29 illustrates the timing relationship between perst_n and the LTSSM L0s state ...

Page 113

... Note to Table 5–8: (1) These signals are not available for the hard IP implementation in Arria II GX devices. (2) The Avalon-ST rx_st_err<n> described in (3) This signal applies only when ECC is enabled in some hard IP configurations. Refer to PCI Express Interrupts for Endpoints Table 5–9 describes the IP core’s interrupt signals for endpoints. ...

Page 114

... MSI allocated ■ 101: 32 MSI allocated ■ 110: Reserved ■ 111: Reserved ■ Multiple message capable: This field is read by system software to determine the number of requested MSI messages. 000: 1 MSI requested ■ 001: 2 MSI requested ■ 010: 4 MSI requested ■ 011: 8 MSI requested ■ ...

Page 115

... MSI. System Error: This signal only applies to hard IP root port designs that report each system error detected by the IP core, assuming the proper enabling bits are asserted in the root O control register and the device control register ...

Page 116

... Table 5–13. Configuration Space Signals (Hard IP Implementation) (Part Signal Width Dir Description Write signal. This signal toggles when tl_cfg_ctl has been updated (every core_clk cycles). The toggle edge marks where the tl_cfg_ctl data changes. You tl_cfg_ctl_wr can use this edge as a reference for determining when the data is safe to sample. ...

Page 117

... Figure 5–33 illustrates the timing of the tl_cfg_sts interface for the Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 128-bit interface. Figure 5–33. tl_cfg_sts Timing (Hard IP Implementation) core_clk pld_clk 128-bit mode tl_cfg_sts[52:0] tl_cfg_sts_wr December 2010 Altera Corporation ...

Page 118

... In the example design created with the PCI Express IP core, there is a Verilog HDL module or VHDL entity included in the altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd files respectively that you can use to sample the configuration space signals. In this module or entity the tl_cfg_ctl_wr and tl_cfg_sts_wr signals are registered twice and then the edges of the delayed signals are used to enable sampling of the tl_cfg_ctl and tl_cfg_sts busses ...

Page 119

... Chapter 5: IP Core Interfaces Avalon-ST Interface Table 5–14. Configuration Space Signals (Hard IP Implementation) (Part Signal Width Dir Description Configuration status bits. This information updates every pld_clk cycle. The cfg_sts group consists of (from MSB to LSB tl_cfg_sts The hpg_ctrler signals are only available in root port mode and when the ...

Page 120

... The tl_cfg_ctl signal is a multiplexed bus that contains the contents of configuration space registers as shown in is accessed in round robin order where tl_cfg_add indicates which register is being accessed. Table 5–15 multiplexed on tl_cfg_ctl. Table 5–15. Multiplexed Configuration Register Information Available on tl_cfg_ctl (Part Address 31:24 cfg_devcsr[15:0] 0 cfg_devcsr[14:12]= ...

Page 121

... Chapter 5: IP Core Interfaces Avalon-ST Interface Table 5–15. Multiplexed Configuration Register Information Available on tl_cfg_ctl (Part Address 31:24 F 16’h0000 Note to Table 5–15: (1) Items in blue are only available for root ports. (2) This field is encoded as specified in Section 7.8.4 of the Table 5–16 describes the configuration space registers referred to in Table 5– ...

Page 122

... Table 5–16. Configuration Space Register Descriptions (Part Register Width Dir 8 O cfg_rootcsr 16 O cfg_seccsr 8 O cfg_secbus 8 O cfg_subbus 20 O cfg_io_bas 20 O cfg_io_lim 12 O cfg_np_bas 12 O cfg_np_lim 44 O cfg_pr_bas 12 O cfg_pr_lim 32 O cfg_pmcsr 16 O cfg_msixcsr PCI Express Compiler User Guide Description Root control and status register of the PCI-Express capability ...

Page 123

... Mapping for TC6. cfg_tcvcmap[23:21]: Mapping for TC7. Configuration bus device: This signal generates a transaction ID for each transaction layer packet, and indicates the bus and device number of the IP core. Because the IP core only implements one function, the function number of the transaction ID must be set to 000b. O cfg_busdev[12:0] cfg_busdev[12:5]: Bus number ...

Page 124

... O cfg_linkcsr[31:0] details. LMI Signals—Hard IP Implementation LMI writes log error descriptor information in the AER header log registers. These writes record completion errors as described in ST Interface” on page Altera does not recommend using the LMI bus to access other configuration space registers for the following reasons: ■ ...

Page 125

... Enable for the PCIe Reconfig option on the System Settings page of the MegaWizard interface. You can use this interface to change the value of configuration registers that are read-only at run time. For a description of the registers available via this interface refer to the section entitled, Cancellation ...

Page 126

... Endpoint—This signal is asserted when the endpoint receives the PME_turn_off message from the root port. For the soft IP implementation asserted until pme_to_cr is asserted. For the hard IP implementation asserted for one cycle. Power management capabilities register. This register is read-only and provides information related to power management for a specific function ...

Page 127

... I Endpoint—initiates a a power_management_event message (PM_PME) that is sent to the root port. If the IP core low power state, the link exists from the low-power state to send the message. This signal is positive edge-sensitive. Power Management Data. This signal is only available in the hard IP implementation. ...

Page 128

... When the application detects an error, it can assert the appropriate cpl_err bit to indicate to the IP core what kind of error to log. If separate requests result in two errors, both are logged. For example completer abort and a completion timeout occur, cpl_err[2] and cpl_err[0] are both asserted for one cycle ...

Page 129

... Specification . Many cases of unsupported requests are detected and reported internally by the transaction layer of the IP core. For a list of these cases, refer to “Errors Detected by the Transaction Layer” on page cpl_err[5]: Unsupported request error for non-posted TLP. The application ■ ...

Page 130

... Refer to the “LMI Signals—Hard IP Implementation” on page 5–40 information about LMI signalling. For the ×8 soft IP, only bits [3:1] of cpl_err are available. For the ×1, ×4 soft IP implementation and all widths of the hard IP implementation, all bits are available. TLP Header corresponding to a cpl_err. Logged by the IP core when cpl_err[6] is asserted. This signal is only available for the × ...

Page 131

... Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and Arria GX. For Stratix IV GX, <n> for ×1 and ×4 IP cores and <n> the ×8 IP core. (2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> For Stratix IV GX, < ...

Page 132

... Figure 5–41 shows the signals of a completer-only, single dword, PCI Express IP core. Figure 5–41. Signals in the Completer-Only, Single Dword, IP Core with Avalon-MM Interface RxmWrite_o RxmRead_o RxmAddress_o[31:0] RxmWriteData_o[31:0] 32-Bit RxmByteEnable_o[3:0] Avalon-MM Rx RxmWaitRequest_i Master Port RxmReadDataValid_i RxmReadData_i[31:0] RxmIrq_i RxmResetRequest_o refclk Clock clk125_out ...

Page 133

... Chapter 5: IP Core Interfaces Avalon-MM Application Interface Table 5–24 lists the interfaces for these IP cores with links to the sections that describe each. Table 5–24. Signal Groups in the PCI Express Variants—Avalon-MM Interface Full Signal Group Featured v Avalon-MM CRA Slave v Avalon-MM RX Master ...

Page 134

... Asserted by the external Avalon-MM slave to hold data transfer. Read data returned from Avalon-MM slave in response to a read request. I This data is sent to the IP core through the TX interface. <n> for the full-featured IP core. <n> for the completer-only, single dword IP core. Asserted by the system interconnect fabric to indicate that the read data valid ...

Page 135

... Avalon Configuration page, the PCI Express I protocol layers are driven by an internal clock that is generated from refclk. This clock is exported by the PCI Express IP core. It can be used for logic outside of the IP core not visible to SOPC Builder O and cannot be used to drive other Avalon-MM components in the system ...

Page 136

... Module Reset_n Note to figure (1) The system-wide reset, reset_n indirectly resets all PCI Express IP core circuitry not affected by PCIe_rstn using the Reset_n_pcie signal and the Reset Synchronizer module. (2) For a description of the dl_ltssm[4:0] bus, refer to Pcie_rstn also resets the rest of the PCI Express IP core, but only after the following synchronization process: 1 ...

Page 137

... The reset_request signal deasserts after Reset_n_pcie asserts. The system-wide reset, reset_n, resets all PCI Express IP core circuitry not affected by Pcie_rstn. However, the reset logic first intercepts the asynchronous reset_n, synchronizes it to the Avalon-MM clock, and sends a reset pulse, Reset_n_pcie to the PCI Express Compiler IP core ...

Page 138

... Stratix IV GX devices. When asserted, indicates that offset calibration is calibrating the transceiver. This signal is used in the hard IP implementation for Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices. This signal keeps the altgxb_reconfig block in reset till the reconfig_clk and fixedclk are stable. Table 5– ...

Page 139

... Note to Table 5–32: (1) The ×1 IP core only has lane 0. The ×4 IP core only has lanes 0–3. For the soft IP implementation of the ×1 IP core any channel of any transceiver block can be assigned for the serial input and output signals. For the hard IP implementation of the ×1 IP core the serial input and output signals must use channel 0 of the Master Transceiver Block associated with that hard IP block. For the × ...

Page 140

... PIPE Interface Signals The ×1 and ×4 soft IP implementation of the IP core is compliant with the 16-bit version of the PIPE interface, enabling use of an external PHY. The ×8 soft IP implementation of the IP core is compliant with the 8-bit version of the PIPE interface. ...

Page 141

... O 1'b1: -3.5 dB ■ The PCI Express IP core hard IP sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value. Receive data <n> (2 symbols on lane <n>). This bus receives data on lane < ...

Page 142

... Table 5–33: (1) where <n> is the lane number ranging from 0-7 (2) For variants that use the internal transceiver, these signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating. Test Signals The test_in and test_out busses provide run-time control and monitoring of the internal state of the IP cores ...

Page 143

... Compliance mode test switch. When set to 1, the IP core is in compliance mode which is used for Compliance Base Board testing (CBB) testing. When set to 0, the IP core is in operates normally. Connect this signal to a switch to turn on and off compliance mode. ...

Page 144

... The test_out bus allows you to monitor the PIPE interface When you choose the 9-bit test_out bus width, a subset of the test_out signals are brought out as follows: bits[4:0] = test_out[4:0] on the ×8 IP core. ...

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... Virtual channel arbitration table 0x200:0x23C Port VC0 arbitration table (Reserved) 0x240:0x27C Port VC1 arbitration table (Reserved) 0x280:0x2BC Port VC2 arbitration table (Reserved) December 2010 Altera Corporation 6. Register Descriptions depending on the version you specify 23:16 15:8 Table 6–2 for details.) Table 6–3 for details.) Table 6– ...

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... In the following tables, the names of fields that are defined by parameters in the parameter editor are links to the description of that parameter. These links appear as green text. Table 6–2. PCI Type 0 Configuration Space Header (Endpoints), Rev2 Spec: Type 0 Configuration Space Header ...

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... Chapter 6: Register Descriptions Configuration Space Register Content Table 6–3 describes the type 1 configuration settings. Table 6–3. PCI Type 1 Configuration Space Header (Root Ports) , Rev2 Spec: Type 1 Configuration Space Header Byte Offset 31:24 0x0000 0x004 0x008 0x00C BIST 0x010 0x014 Secondary Latency ...

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... Rev2 Spec: PCI Express Capabilities 23:16 Next Cap Pointer Device Capabilities Device Status Link Capabilities Link Status Slot Capabilities Slot Status Reserved Root Status Chapter 6: Register Descriptions Configuration Space Register Content 15:8 7:3 2:0 Capability ID BIR PCI Express 15:8 7:0 Cap ID ...

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... Chapter 6: Register Descriptions Configuration Space Register Content Table 6–8 describes the PCI Express capability structure for specification version 2.0. Table 6–8. PCI Express Capability Structure Version 2.0, Rev2 Spec: PCI Express Capabilities Register and PCI Express Capability List Register Byte Offset ...

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... Avalon-MM processors only, or from both types of processors. Because all accesses come across the system interconnect fabric —requests from the PCI Express IP core are routed through the interconnect fabric— hardware does not enforce restrictions to limit individual processor access to specific regions. However, the regions are designed to enable straight-forward enforcement by processor software ...

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... Chapter 6: Register Descriptions PCI Express Avalon-MM Bridge Control Register Content The four subregions are described Table 6–11. Avalon-MM Control and Status Register Address Spaces Address Range Registers typically intended for access by PCI Express processors only. This includes PCI Express 0x0000-0x0FFF interrupt enable controls, Write access to the PCI Express Avalon-MM bridge mailbox registers, and read access to Avalon-MM-to-PCI Express mailbox registers ...

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... Description — — Enables generation of PCI Express interrupts when a RW specified mailbox is written external Avalon- MM master. — — Enables generation of PCI Express interrupts when RW RXmlrq_i is asserted — — December 2010 Altera Corporation Chapter 6: Register Descriptions Address: 0x0040 “Generation of PCI Address: 0x0050 ...

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... Chapter 6: Register Descriptions PCI Express Avalon-MM Bridge Control Register Content The PCI Express-to-Avalon-MM mailbox registers are writable at the addresses shown in Table 6–15. Writing to one of these registers causes the corresponding bit in the Avalon-MM interrupt status register to be set to a one. Table 6–15. PCI Express-to-Avalon-MM Mailbox Registers, Read/Write ...

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... These registers must not be accessed by the PCI Express Avalon-MM bridge master ports; however, there is nothing in the hardware that prevents this. PCI Express Compiler User Guide Chapter 6: Register Descriptions PCI Express Avalon-MM Bridge Control Register Content (Table Address Range: 0x1000-0x1FFF ...

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... Chapter 6: Register Descriptions PCI Express Avalon-MM Bridge Control Register Content The interrupt status register cause an Avalon-MM interrupt to be asserted. Table 6–19. PCI Express to Avalon-MM Interrupt Status Register Bits Name [15:0] Reserved [16] P2A_MAILBOX_INT0 [17] P2A_MAILBOX_INT1 [18] P2A_MAILBOX_INT2 [19] P2A_MAILBOX_INT3 [20] P2A_MAILBOX_INT4 [21] P2A_MAILBOX_INT5 [22] P2A_MAILBOX_INT6 [23] P2A_MAILBOX_INT7 [31:24] Reserved ...

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... PCIe Spec Rev 2.0 Table 6–23 provides a comprehensive correspondence between the configuration space registers and their descriptions in the Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 Table 6-1. ...

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... Chapter 6: Register Descriptions Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0 Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 0x0B8:0x0FC Reserved 0x094:0x0FF Root port ...

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... Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 0x014 Base Address 1 Secondary Latency Timer Subordinate Bus 0x018 Number Secondary Bus Number Primary Bus Number 0x01C ...

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... Chapter 6: Register Descriptions Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0 Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 Table 6-8. PCI Express Capability Structure Version 2.0, Rev2 Spec: PCI Express Capabilities Register and PCI Express ...

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... Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 0x800 PCI Express Enhanced Capability Header 0x804 Uncorrectable Error Status Register 0x808 Uncorrectable Error Mask Register 0x80C ...

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... PCI Express IP core. The _plus variant includes all of the logic necessary to initialize the PCI Express IP core, including the following: December 2010 Altera Corporation 7. Reset and Clocks Interfaces: “ ...

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... Refer to Figure 7–2 for more detail on this variant. f Refer to “PCI Express (PIPE) Reset Sequence” in the chapter in volume of volume 2 of the Stratix IV Device Handbook for a timing diagram illustrating the reset sequence understand the reset sequence in detail, you can also review altpcie_rs_serdes.v file ...

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... For designs that use the internal ALTGX transceiver, the PIPE interface is transparent. You can use the reset sequence provided for the hard IP implementation in the <variant>_rs_hip.v or .vhd IP core as a reference in designing your own circuit. In addition, to understand the domain of each reset signal, refer to Domains, Hard IP and × ...

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... Figure 7–3: (1) The Gen1 ×8 does not include the crst signal and rstn replaces srst in the soft IP implementation. (2) The dlup_exit signal should cause the application to assert srst, but not crst. (3) gxb_powerdown stops the generation of core_clk_out for hard IP implementations and clk125_out for soft IP implementations. ...

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... Link Training Signals” on page To meet 100 ms PCIe configuration time, a reset controller implemented as a hard macro handles the initial reset of the PMA, PCS, and PCI Express IP core. Once the PCI Express link has been established, a soft reset controller handles warm and hot resets. The < ...

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... For endpoints, whenever the l2_exit, hotrst_exit, dlup_exit, or other power-on-reset signals are asserted, srst and crst should be asserted for one or more cycles for the soft IP implementation and for at least two clock cycles for hard IP implementation. Figure 7–5 provides a simplified view of the logic controlled by the reset signals. ...

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... When the perst# signal is asserted, rstn should be asserted for a longer period of time to ensure that the root complex is stable and ready for link training. Clocks This section describes clocking for the PCI Express IP core. It includes the following sections: ■ Avalon-ST Interface—Hard IP Implementation Avalon-ST Interface— ...

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... PHY/MAC and the DLL layers which allows the data link and transaction layers to run at frequencies independent of the PHY/MAC and provides more flexibility for the user clock interface to the IP core. Depending on system requirements, this additional flexibility can be used to enhance performance by running at a higher frequency for latency optimization lower frequency to save power ...

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... Gen2. The PCI Express specification allows a +/- 300 ppm variation on the clock frequency. The CDC module implements the asynchronous clock domain crossing between the PHY/MAC p_clk domain and the data link layer core_clk domain. December 2010 Altera Corporation PCI Express Hard IP - Three Clock Domains Clock Data Link Domain PHY ...

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... There are two clock input signals: refclk and either clk125_in for x1 or ×4 variations or clk250_in for ×8 variations. The ×1 and ×4 IP cores also have an output clock, clk125_out, that is a 125 MHz transceiver clock. For external PHY variations clk125_out is driven from the refclk input. The × ...

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... Refer to Table 7–1 on page 7–10 When you implement a generic PIPE PHY in the IP core, you must provide a 125 MHz clock on the clk125_in input. Typically, the generic PIPE PHY provides the 125 MHz clock across the PIPE interface. All of the IP core interfaces, including the user application interface and the PIPE interface, are synchronous to the clk125_in input ...

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... MegaCore Function) Transceivers in Volume 2 of the Stratix IV Device Handbook, or Chapter 7: Reset and Clocks Clocks clk62.5_out or clk125_out Application C Transceiver in Volume 2 of the Cyclone IV Device Altera PHY IP User Guide for December 2010 Altera Corporation ...

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... MegaCore Function) clk250_in Transceivers in Volume 2 of the Stratix IV Device Handbook, or 7–13 clk250_out Application Clock Transceiver in Volume 2 of the Cyclone IV Device Altera PHY IP User Guide for PCI Express Compiler User Guide ...

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... When you turn on the page of the parameter editor, the system clock source, labeled ref_clk in is external to the PCI Express IP core. The protocol layers of the IP core are driven by an internal clock that is generated from the reference clock, ref_clk. The PCI Express IP core exports a 125 MHz clock, clk125_out, which can be used for logic outside the IP core ...

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... Chapter 7: Reset and Clocks Clocks The system interconnect fabric drives the additional input clock, clk in the PCI Express IP core. In general, clk is the main clock of the SOPC Builder system and originates from an external clock source. Figure 7–12. SOPC Builder - Separate Clock Domains ...

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... Description In this clocking mode, the PCI Express IP core provides a 125 MHz clock output to be used as a system clock and the IP core protocol layers operate on the same clock. This clock is visible to SOPC Builder and can be selected as the clock source for any Avalon-MM component in the system. In this clocking mode, the PCI Express IP core’ ...

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... December 2010 <edit Part Number variable in chapter> This chapter provides detailed information about the PCI Express IP core. TLP handling. It includes the following sections: Supported Message Types ■ ■ Transaction Layer Routing Rules ■ Receive Buffer Reordering Supported Message Types Table 8–1 describes the message types supported by the IP core. Table 8– ...

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... No As per the recommendations in the No Yes No Base Specification Revision 1.1 or 2.0 messages are not transmitted to the application No Yes No layer in the hard IP implementation. For soft IP implementation, following the PCI No Yes No Express Specification 1.0a, these messages are No Yes No transmitted to the application layer. No Yes ...

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... In endpoint mode, received type 0 configuration requests from the PCI Express upstream port route to the internal configuration space and the IP core generates and transmits the completion. In root port mode, the application can issue type 0 or type 1 configuration TLPs on ■ ...

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... The IP core can generate and transmit power management, interrupt, and error ■ signaling messages automatically under the control of dedicated signals. Additionally, the IP core can generate MSI requests under the control of the dedicated signals. Receive Buffer Reordering The receive datapath implements a receive buffer reordering function that allows ...

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... Read Completions for Request (same Transaction ID) must return in address order. 1 MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and are indistinguishable from them in terms of flow control, ordering, and data integrity. December 2010 Altera Corporation (Note 1)– (12) Yes ...

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... PCI Express Compiler User Guide Chapter 8: Transaction Layer Protocol (TLP) Details Receive Buffer Reordering December 2010 Altera Corporation ...

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... Capabilities page of the MegaWizard Plug-In Manager. The ECRC function includes the ability to check and generate ECRC for all PCI Express IP cores. The hard IP implementation can also forward the TLP with ECRC to the receive port of the application layer. The hard IP implementation transmits a TLP with ECRC from the transmit port of the application layer ...

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... ECRC Forwarding No Yes Notes to Table 9–2: (1) All unspecified cases are unsupported and the behavior of the IP core is unknown. (2) The ECRC Generation Enable is in the configuration space advanced error capabilities and control register. PCI Express Compiler User Guide ECRC ECRC Check Error Status ...

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... An endpoint can exit the L0s or L1 state by asserting the pm_pme signal. Doing so, initiates a power_management_event message which is sent to the root complex. If the IP core is in theL0s or L1 state, the link exits the low-power state to send this message. The pm_pme signal is edge-senstive. If the link is in the L2 state, a Beacon (or Wake#) is generated to reinitialize the link before the core can generate the power_management_event message ...

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... Power State L0s exit latency is calculated by the IP core based on the number of fast training sequences specified on the Power Management page of the MegaWizard Plug-In Manager maintained in a configuration space registry. Main power and the reference clock remain present and the PHY should resynchronize quickly for receive data ...

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... Connected PCI Express components need not support the same number of lanes. The ×4 and ×8 IP core in both soft and hard variations support initialization and operation with components that have lanes. The ×8 IP core in both soft and hard variations supports initialization and operation with components that have lanes ...

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... Whether you use the MegaWizard Plug-In Manager or the SOPC Builder design flow, you must ensure that the cal_blk_clk input to each PCI Express IP core (or any other megafunction or user logic that uses the ALTGX or ALT2GXB megafunction) is driven by the same calibration clock source ...

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... In the MegaWizard Plug-In Manager flow, the script contains virtual pins for most I/O ports on the PCI Express IP core to ensure that the I/O pin count for a device is not exceeded. These virtual pin assignments must reflect the names used to connect to each PCI Express instantiation. ...

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... PCI Express Compiler User Guide Chapter 9: Optional Features Instantiating Multiple PCI Express IP Cores December 2010 Altera Corporation ...

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... MSI-X interrupts when configured in endpoint mode. MSI-X interrupts are only available in the hard IP implementation endpoint variations. The MSI, MSI-X, and legacy interrupts are mutually exclusive. After power up, the IP core starts in INTX mode, after which time software decides whether to switch to MSI mode by ...

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... R/W app_int_sts1 Figure 10–3, the endpoint requests eight MSIs but is only Root Complex Root Endpoint Port 8 Requested 2 Allocated Interrupt Register Chapter 10: Interrupts MSI Interrupts app_int_sts msi_enable & Master Enable app_msi_req MSI app_msi_ack Arbitration CPU Interrupt Block December 2010 Altera Corporation ...

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... Legacy Interrupts Legacy interrupts are signaled on the PCI Express link using message TLPs that are generated internally by the PCI Express IP core. The app_int_sts input port controls interrupt generation. When the input port asserts app_int_sts, it causes an Assert_INTA message TLP to be generated and sent upstream. Deassertion of the app_int_sts input port causes a Deassert_INTA message TLP to be generated and sent upstream ...

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... For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data. PCI Express Interrupts for Root Ports In root port mode, the PCI Express IP core receives interrupts through two different mechanisms: ■ ...

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... Posted Data Non-Posted Headers ■ ■ Non-Posted Data ■ Completion Headers ■ Completion Data December 2010 Altera Corporation 11–2. This section discusses the Flow Control 11–1. If the requester of the writes sources the data as quickly as 11. Flow Control PCI Express Compiler User Guide ...

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... Physical Data Link Express Layer Layer Layer Link Figure 11–1 show the general area to which they Chapter 11: Flow Control Throughput of Posted Writes FC Update Credit DLLP Allocated Incr Data Packet Buffer Transaction App Layer Layer Layer Data Sink December 2010 Altera Corporation ...

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... TLP transmitted. Table 11–1 shows the delay components for the FC Update Loop when the PCI Express IP core is implemented in a Stratix II GX device. The delay components are independent of the packet length. The total delays in the loop increase with packet length. ...

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... However, much of the delay encountered in this loop is well outside the PCI Express IP core and is very difficult to estimate. PCI Express switches can be inserted in this loop, which makes determining a bound on the delay more difficult. ...

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... Nevertheless, maintaining maximum throughput of completion data packets is important. PCI Express endpoints must offer an infinite number of completion credits. The PCI Express IP core must buffer this data in the RX buffer until the application can process it. Because the PCI Express IP core is no longer managing the RX buffer through the flow control mechanism, the application must manage the RX buffer by the rate at which it issues read requests ...

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... The number of header tag values that can be in use is also limited by the PCI Express IP core. For the ×8 function, you can specify 32 tags. For the ×1 and ×4 functions, you can specify up to 256 tags, though configuration software can restrict the application to use only 32 tags ...