IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 288

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

16–4
Parameterize the PCI Express IP core
PCI Express Compiler User Guide
1
This example design requires that you specify the same name for the SOPC Builder
system as for the top-level project file. However, this naming is not required for your
own design. If you want to choose a different name for the system file, you must
create a wrapper HDL file of the same name as the project's top level and instantiate
the generated system.
3. To add modules from the System Contents tab, under Interface Protocols in the
To parameterize the PCI Express IP core in SOPC Builder, follow these steps:
1. On the System Settings page, specify the settings in
Table 16–1. System Settings Parameters
2. On the PCI Registers page, specify the settings in
Table 16–2. PCI Registers Parameters
3. Click the Avalon page and specify the settings in
Table 16–3. Avalon Parameters
Parameter
PCIe Core Type
PHY type
Lanes
PCI Express version
Test out width
BAR
1:0
2
Device ID
Vendor ID
Parameter
Avalon Clock Domain
PCIe Peripheral Mode
Address Translation Table Size
Number of address pages
Size of address pages
PCI folder, double-click the PCI Express Compiler<version_number> component.
For an example of a system that uses the PCI Express core clock for the Avalon
clock domain see
BAR Type
64-bit Prefetchable Memory
32-bit Non-Prefetchable Memory
PCI Base Address Registers (Type 0 Configuration Space)
Figure 7–13 on page
Address Translation Table Size
7–15.
BAR Size
Value
Use separate clock
Requester/Completer
Dynamic translation table
2
1 MByte - 20 bits
Value
PCI Express hard IP
Stratix IV GX
×4
1.1
9 bits
Table
0xE001
0x1172
Table
Chapter 16: SOPC Builder Design Example
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Table
16–3.
Parameterize the PCI Express IP core
16–2.
December 2010 Altera Corporation
16–1.
Avalon Base Address
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