IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 119

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–14. Configuration Space Signals (Hard IP Implementation) (Part 2 of 2)
December 2010 Altera Corporation
Signal
tl_cfg_sts
hpg_ctrler
Width Dir Description
53
5
[0]
[1]
[2]
[3]
[4]
0
I
I
I
I
I
I
Configuration status bits. This information updates every pld_clk cycle. The cfg_sts
group consists of (from MSB to LSB):
The hpg_ctrler signals are only available in root port mode and when the
capability
register
input should be hardwired to 0's. The bits have the following meanings:
Attention button pressed. This signal should be asserted when the attention button is
pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and
the Attention Button Present bit (bit[0]) in the
should be set to 0.
Presence detect. This signal should be asserted when a presence detect change is
detected in the slot via a presence detect circuit.
Manually-operated retention latch (MRL) sensor changed. This signal should be
asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does
not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor Present
bit (bit[2]) in the
Power fault detected. This signal should be asserted when the power controller detects
a power fault for this slot. If there is not a power controller for this slot this bit should
be hardwired to 0, and the Power Controller Present bit (bit[1]) in the
capability register
Power controller status. This signal is used to set the command completed bit of the
Slot Status register. Power controller status is equal to the power controller control
signal. If there is not a power controller for this slot, this bit should be hardwired to 0
and the Power Controller Present bit (bit[1]) in the
parameter should be set to 0.
tl_cfg_sts[52:49]= cfg_devcsr[19:16]error detection signal as follows:
[correctable error reporting, enable, non-fatal error reporting
enable, fatal error reporting enable, unsupported request
reporting enable]
tl_cfg_sts[48] = cfg_slotcsr[24]Data link layer state changed
tl_cfg_sts[47]= cfg_slotcsr[20]Command completed
tl_cfg_sts[46:31] = cfg_linkcsr[31:16]Link status bits
tl_cfg_sts[30] = cfg_link2csr[16]Current de-emphasis level.
cfg_link2csr[31:17] are reserved per the PCIe Specification and are not
available on tl_cfg_sts bus
tl_cfg_sts[29:25] = cfg_prmcsr[31:27]5 primary command status error bits
tl_cfg_sts[24] = cfg_prmcsr[24]6th primary command status error bit
tl_cfg_sts[23:6] = cfg_rootcsr[25:8]PME bits
tl_cfg_sts[5:1]= cfg_seccsr[31:27] 5 secondary command status error bits
tl_cfg_sts[0] = cfg_seccsr[4] 6th secondary command status error bit
parameters in
parameter is set to On. Refer to the
Slot capability register
parameter should be set to 0.
Table 3–3 on page
parameter should be set to 0.
3–7. For endpoint variations the hpg_ctrler
Enable slot capability
Slot capability register
Slot capability register
PCI Express Compiler User Guide
and
Slot capability
Enable slot
Slot
parameter
5–35