IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 225

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 14: External PHYs
External PHY Support
Table 14–2. 16-bit PHY Interface Signals (Part 3 of 3)
Table 14–3. 8-bit PHY Interface Signals (Part 1 of 2)
December 2010 Altera Corporation
rxelecidle3_ext
rxpolarity3_ext
rxstatus3_ext[1:0]
rxvalid3_ext
txcompl3_ext
txdata3_ext[15:0]
txdatak3_ext[1:0]
txelecidle3_ext
pcie_rstn
phystatus_ext
powerdown_ext[1:0]
refclk
pipe_txclk
rxdata0_ext[7:0]
rxdatak0_ext
rxelecidle0_ext
rxpolarity0_ext
rxstatus0_ext[1:0]
rxvalid0_ext
txcompl0_ext
txdata0_ext[7:0]
txdatak0_ext
txelecidle0_ext
rxdata1_ext[7:0]
Signal Name
Signal Name
8-bit PHY Interface Signals
Table 14–3
Depending on the number of lanes selected and whether the PHY mode has a TXClk,
some of the signals may not be available as noted.
Direction
Direction
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
summarizes the external I/O signals for the 8-bit PIPE interface modes.
PCI Express reset signal, active low.
PIPE interface phystatus signal. Signals the completion
of the requested operation.
PIPE interface powerdown signal, Used to request that
the PHY enter the specified power state.
Input clock connected to the PIPE interface pclk signal
from the PHY. Clocks all of the status and data signals.
Depending on whether this is an SDR or DDR interface
this clock will be either 250 MHz or 125 MHz.
Source synchronous transmit clock signal for clocking
TX data and control signals going to the PHY.
Pipe interface lane 0 RX data signals, carries the parallel
received data.
Pipe interface lane 0 RX data K-character flag.
Pipe interface lane 0 RX electrical idle indication.
Pipe interface lane 0 RX polarity inversion control.
Pipe interface lane 0 RX status flags.
Pipe interface lane 0 RX valid indication.
Pipe interface lane 0 TX compliance control.
Pipe interface lane 0 TX data signals, carries the parallel
transmit data.
Pipe interface lane 0 TX data K-character flag.
Pipe interface lane 0 TX electrical idle control.
Pipe interface lane 1 RX data signals, carries the parallel
received data.
Pipe interface lane 3 RX electrical idle indication.
Pipe interface lane 3 RX polarity inversion control.
Pipe interface lane 3 RX status flags.
Pipe interface lane 3 RX valid indication.
Pipe interface lane 3 TX compliance control.
Pipe interface lane 3 TX data signals, carries the
parallel transmit data.
Pipe interface lane 3 TX data K-character flags.
Pipe interface lane 3 TX electrical Idle Control.
Description
Description
PCI Express Compiler User Guide
Always
Always
Always
Always
Only in modes that
have the TXClk
Always
Always
Always
Always
Always
Always
Always
Always
Always
Always
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Availability
Availability
14–9