IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 128

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–44
Table 5–22. Power Management Capabilities Register Field Descriptions (Part 2 of 2)
PCI Express Compiler User Guide
[12:9]
[8]
[7:2]
[1:0]
Bits
Completion Side Band Signals
data_select
PME_EN
reserved
PM_state
Field
Figure 5–39
the IP core receives the PME_turn_off message which causes pme_to_sr to assert.
Then, the application sends the PME_to_ack message to the root port by asserting
pme_to_cr.
Figure 5–39. pme_to_sr and pme_to_cr in an Endpoint IP core
Table 5–23
Avalon-ST interface. The IP core provides a completion error interface that the
application can use to report errors, such as programming model errors, to it. When
the application detects an error, it can assert the appropriate cpl_err bit to indicate to
the IP core what kind of error to log. If separate requests result in two errors, both are
logged. For example, if a completer abort and a completion timeout occur, cpl_err[2]
and cpl_err[0] are both asserted for one cycle. The IP core sets the appropriate status
bits for the error in the configuration space, and automatically sends error messages
in accordance with the
responsible for sending the completion with the appropriate completion status value
for non-posted requests. Refer to
errors that are automatically detected and handled by the IP core.
hard
soft
IP
IP
This field indicates which data should be reported through the data register and the
data_scale field.
1: indicates that the function can assert PME#
0: indicates that the function cannot assert PME#
Specifies the power management state of the operating condition being described.
Defined encodings are:
■
■
■
■
A device returns 2b’11 in this field and Aux or PME Aux in the type register to specify the
D3-Cold PM state. An encoding of 2b’11 along with any other type register value
specifies the D3-Hot state.
describes the signals that comprise the completion side band signals for the
illustrates the behavior of pme_to_sr and pme_to_cr in an endpoint. First,
2b’00 D0
2b’01 D1
2b’10 D2
2b’11 D
pme_to_sr
pme_to_cr
pme_to_sr
pme_to_cr
clk
PCI Express Base
Chapter 12, Error Handling
Specification. Note that the application is
Description
—
December 2010 Altera Corporation
for information on
Chapter 5: IP Core Interfaces
Avalon-ST Interface