IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 147

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
Configuration Space Register Content
Table 6–3. PCI Type 1 Configuration Space Header (Root Ports) , Rev2 Spec: Type 1 Configuration Space Header
Table 6–4. MSI Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
December 2010 Altera Corporation
0x0000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Note to
(1) Refer to
0x050
0x054
0x058
0x05C
Note to
(1) Refer to
Byte Offset
Base Specification 2.0.
Base Specification 2.0.
Byte Offset
Table
Table
Table 6–23 on page 6–12
Table 6–23 on page 6–12
6–3:
6–4:
Reserved
Expansion ROM Base Address
Secondary Latency
Table 6–3
Table 6–4
Configuration MSI Control Status Register Field
Timer
Prefetchable Memory Limit
31:24
BIST
I/O Limit Upper 16 Bits
for a comprehensive list of correspondences between the configuration space registers and the
31:24
for a comprehensive list of correspondences between the configuration space registers and the
describes the type 1 configuration settings.
describes the MSI capability structure.
Secondary Status
Bridge Control
Memory Limit
Message Control
Device ID
Descriptions
Status
Reserved
Header Type
Subordinate Bus
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Class code
Number
23:16
23:16
Message Upper Address
BAR Table (BAR0)
BAR Table (BAR1)
Message Address
I/O Base Upper 16 Bits
Primary Latency
Secondary Bus
Interrupt Pin
Next Cap Ptr
I/O Limit
Number
Timer
Prefetchable Memory Base
15:8
15:8
Memory Base
Message Data
Vendor ID
Command
PCI Express Compiler User Guide
Cache Line Size
Primary Bus Number
Interrupt Line
Capability ID
Capabilities
Revision ID
I/O Base
Pointer
7:0
7:0
PCI Express
PCI Express
6–3