IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 327

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–18. TX Inserting Wait States because of 4-DWORD Header Waveform
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[63:32]
In clock cycle 3, the IP core inserts a wait state because the memory write 64-bit
transaction layer packet request has a 4-DWORD header. In this case, tx_dv could
have been sent one clock cycle later.
Priority Given Elsewhere
In this example, the application transmits a 64-bit memory write transaction of 8
DWORDS. Address bit 2 is set to 0. The transmit path has a 3-deep, 64-bit buffer to
handle back-to-back transaction layer packets as fast as possible, and it accepts the
tx_desc and first tx_data without delay. Refer to
tx_ack
tx_req
tx_dfr
tx_ws
tx_err
tx_dv
clk
1
2
3
DW 0
4
5
DW 2
DW 1
Figure
6
DW 4
DW 3
B–19.
7
DW 6
DW 5
PCI Express Compiler User Guide
8
DW 7
9
B–21