IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 102

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–18
Figure 5–16. 64-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with Non-QWord Aligned Address
Notes to
(1) Header0 ={pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr_byte4, pcie_hdr _byte5, header pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(5) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
(6) Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8}.
Figure 5–17. 64-Bit Avalon-ST tx_st_data Cycle Definition for 4–DWord TLP with QWord Aligned Address
Notes to
(1) Header0 = {pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Header3 = pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15}, 4 dword header only
(5) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
PCI Express Compiler User Guide
Figure
Figure
tx_st_data[63:32]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_data[31:0]
5–16:
5–17:
tx_st_eop
tx_st_eop
tx_st_sop
tx_st_sop
clk
clk
Figure 5–16
TLPs for 3 dword header TLPs with non-qword aligned addresses with a 64-bit bus.
(Figure 5–5 on page 5–9
Figure 5–17
TLPs for a four dword header with qword aligned addresses with a 64-bit bus.
1
1
illustrates the mapping between Avalon-ST TX packets and PCI Express
illustrates the mapping between Avalon-ST TX packets and PCI Express
Header0
Header1
Header0
Header1
illustrates the storage of non-qword aligned data.)
2
2
Header2
Header3
Header2
Data0
3
3
Data2
Data1
Data0
Data1
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface