IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 28
IP-AGX-PCIE/4
Manufacturer Part Number
IP-AGX-PCIE/4
Description
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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2–2
Figure 2–1. System Settings
PCI Express Compiler User Guide
8. Click the Parameter Settings tab. The System Settings page appears. Note that
9.
Table 2–1. System Settings Parameters
PCIe Core Type
PHY type
PHY interface
Configure transceiver block
Lanes
Xcvr ref_clk
Application interface
Port type
PCI Express version
Application clock
Max rate
Test out width
PCIe reconfig
there are three tabs labeled Parameter Settings, EDA, and Summary.
Figure 2–1
Table 2–1
provides the correct System Settings.
specifies the parameters to run the testbench.
Parameter
PCI Express hard IP
Stratix IV GX
100 MHz
Gen 2 (5.0 Gbps)
64 bits
Disable
serial
Use default settings.
Avalon-ST 128 -bit
Native Endpoint
250 MHz
×8
2.0
December 2010 Altera Corporation
Value
Parameterize the PCI Express
Chapter 2: Getting Started
Parameters, EDA Tools
and Summary Tabs
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