IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 152

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–8
Table 6–13. Avalon-MM to PCI Express Interrupt Status Register (Part 2 of 2)
Table 6–14. Avalon-MM to PCI Express Interrupt Enable Register
PCI Express Compiler User Guide
21
20
19
18
17
16
15:14
13:8
7
6:0
[31:24]
[23:16]
[15:8]
[7]
[6:0]
Bit
Bits
PCI Express Mailbox Registers
A2P_MAILBOX_INT5
A2P_MAILBOX_INT4
A2P_MAILBOX_INT3
A2P_MAILBOX_INT2
A2P_MAILBOX_INT1
A2P_MAILBOX_INT0
Reserved
AVL_IRQ_INPUT_VECTOR
AVL_IRQ_ASSERTED
Reserved
Reserved
A2P_MB_IRQ
Reserved
AVL_IRQ
Reserved
A PCI Express interrupt can be asserted for any of the conditions registered in the PCI
Express interrupt status register by setting the corresponding bits in the
Avalon-MM-to-PCI Express interrupt enable register
legacy interrupts can be generated as explained in the section
Express Interrupts” on page
The PCI Express root complex typically requires write access to a set of PCI
Express-to-Avalon-MM mailbox registers and read-only access to a set of
Avalon-MM-to-PCI Express mailbox registers. There are eight mailbox registers
available.
Name
Name
Access
Access
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW
RW
4–22.
—
—
—
RO
RO
—
—
Enables generation of PCI Express interrupts when a
specified mailbox is written to by an external Avalon-
MM master.
Enables generation of PCI Express interrupts when
RXmlrq_i is asserted
1 when the A2P_MAILBOX5 is written to
1 when the A2P_MAILBOX4 is written to
1 when the A2P_MAILBOX3 is written to
1 when the A2P_MAILBOX2 is written to
1 when the A2P_MAILBOX1 is written to
1 when the A2P_MAILBOX0 is written to
Avalon-MM interrupt input vector. When an Avalon-MM
IRQ is being signaled (AVL_IRQ_ASSERTED = 1), this
register indicates the current highest priority
Avalon-MM IRQ being asserted. This value changes as
higher priority interrupts are asserted and deasserted.
This register stores the value of the RXmIrqNum_i input
signal.
Current value of the Avalon-MM interrupt (IRQ) input
ports to the Avalon-MM RX master port:
0 – Avalon-MM IRQ is not being signaled.
1 – Avalon-MM IRQ is being signaled.
PCI Express Avalon-MM Bridge Control Register Content
(Table
Description
Description
December 2010 Altera Corporation
6–14). Either MSI or
—
—
—
—
—
Chapter 6: Register Descriptions
“Generation of PCI
Address: 0x0050
Address: 0x0040