IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 109

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–7. Reset and Link Training Signals (Part 2 of 3)
December 2010 Altera Corporation
perst_n
pld_clk_ready
pld_clk_in_use
reset_status
rstn
npor
srst
crst
pld_clrhip_n
pld_clrpmapcship
l2_exit
hotrst_exit
Signal
I/O
O
O
O
O
I
I
I
I
I
I
I
I
Active low reset from the PCIe reset pin of the device. This pin is required for CvPCIe in
Stratix V devices. Stratix V devices specify a single pin for perst_n in each PCIe hard IP
instance. Refer to the appropriate Stratix V device pin-out for correct pin assigment for each
perst_n pin. The
be 3.3 V. If this signal is used in a bank that requires a lower voltage such as DDR3 running at
1.5 V, you must use a voltage level-shifter on the PCB to convert this signal to 1.5 V.
npor performs the same function for earlier devices. Refer to
timing diagram illustrating the use of this signal.
For Stratix V devices, indicates that the FPGA fabric configuration is complete and that
pld_clk_ready which is stable after CvPCIe completes is ready. Refer to
page 5–28
For Stratix V devices, indicates that the FPGA is using the PLD clock. Refer to
page 5–28
Reset Status signal. When asserted, this signal indicates that the IP core is in reset. This signal
is only available in the hard IP implementation. When the npor or perst_n for Stratix V
signal asserts, reset_status is reset to zero. The reset_status signal is synchronous to
the pld_clk and is deasserted only when the pld_clk is good.
Asynchronous reset of configuration space and datapath logic. Active Low. This signal is only
available on the ×8 IP core. Used in ×8 soft IP implementation only. This signal is not used for
Stratix V devices.
Power on reset. This signal is the asynchronous active-low power-on reset signal. This reset
signal is used to initialize all configuration space sticky registers, PLL, and SERDES circuitry. It
also resets the datapath and control registers. This signal is not used for Stratix V devices.
perst_n performs the same function in Stratix V devices.
Synchronous datapath reset. This signal is the synchronous reset of the datapath state
machines of the IP core. It is active high. This signal is only available on the hard IP and soft IP
×1 and ×4 implementations. This signal is not used for Stratix V devices.
Synchronous configuration reset. This signal is the synchronous reset of the nonsticky
configuration space registers. It is active high. This signal is only available on the hard IP, and
×1 and ×4 soft IP implementations. This signal is not used for Stratix V devices.
Resets all registers PCIe. For Stratix V only.
Resets all registers in the PMA, PCS, and PCIe IP core. For Stratix V only.
L2 exit. The PCI Express specification defines fundamental hot, warm, and cold reset states. A
cold reset (assertion of crst and srst for the hard IP implementation and the ×1 and ×4 soft
IP implementation, or rstn for ×8 soft IP implementation) must be performed when the
LTSSM exits L2 state (signaled by assertion of this signal). This signal is active low and
otherwise remains high. It is asserted for one cycle (going from 1 to 0 and back to 1) after the
LTSSM transitions from l2_idl to detect.
Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset
state. It informs the application layer that it is necessary to assert a global reset (crst and
srst for the hard IP implementation and the ×1 and ×4 soft IP implementation, or rstn for ×8
soft IP implementation). This signal is active low and otherwise remains high. In Gen1 and
Gen2, the hotrst_exit signal is asserted 1 ms after the dl_ltssm signal exit from the
hot.reset state
for a timing diagram illustrating the use of this signal.
for a timing diagram illustrating the use of this signal.
PCI Express Card Electromechanical Specification 2.0
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Description
Figure 5–29 on page 5–28
PCI Express Compiler User Guide
specifies this signal to
Figure 5–28 on
Figure 5–28 on
for a
5–25