IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 223

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 14: External PHYs
External PHY Support
Figure 14–6. 8-bit SDR Mode with 250 MHz Source Synchronous Transmit Clock
Table 14–2. 16-bit PHY Interface Signals (Part 1 of 3)
December 2010 Altera Corporation
pcie_rstn
phystatus_ext
powerdown_ext[1:0]
refclk
Signal Name
16-bit PHY Interface Signals
External connection
clk125_in
clk125_out
in user logic
txclk (~refclk)
rxdata
refclk (pclk) 250 MHz
An edge detect circuit detects the relationships between the 125 MHz clock and the
250 MHz rising edge to properly sequence the 16-bit data into the 8-bit output
register.
Table 14–2
Depending on the number of lanes selected and whether the PHY mode has a TXClk,
some of the signals may not be available as noted.
txdata
Direction
O
I
I
I
summarizes the external I/O signals for the 16-bit PIPE interface modes.
PCI Express reset signal, active low.
PIPE interface phystatus signal.Signals the completion
of the requested operation
PIPE interface powerdown signal. Used to request that
the PHY enter the specified power state.
Input clock connected to the PIPE interface pclk signal
from the PHY. 125 MHz clock that clocks all of the
status and data signals.
Mode 4
A
D
PLL
& Sync
Detect
Edge
ENB
Q
Q
Q
Q
1
4
1
4
ENB
ENB
Q
Q
1
4
A
D
A
D
clk250_early
Description
A
D
A
D
clk250_early
ENB
ENB
Q
Q
1
4
ENB
Q
Q
Q
Q
1
4
1
4
A
D
A
D
A
D
ENB
ENB
Q
Q
Q
Q
1
4
1
4
rxdata_h
rxdata_l
txdata_h
txdata_l
clk125_zero
tlp_clk
refclk
MegaCore Function
PCI Express
PCI Express Compiler User Guide
Always
Always
Always
Always
Availability
14–7