IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 52

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–10
Table 3–3. Capabilities Parameters (Part 4 of 4)
Buffer Setup
Table 3–4. Buffer Setup Parameters (Part 1 of 3)
PCI Express Compiler User Guide
Pending Bit Array
(PBA)
Note to
(1) Throughout The PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the
Maximum
payload size
0x084
Number of
virtual channels
0x104
Number of
low-priority VCs
0x104
Auto configure
retry buffer size
Retry buffer size
Offset
BAR Indicator
(BIR)
Specification Revision 1.0a, 1.1, 2.0 or
Parameter
Parameter
Table
3–3:
None, 1
On/Off
256 Bytes–
16 KBytes
(powers of 2)
128 bytes,
256 bytes,
512 bytes,
1 KByte,
2 KBytes
1–2
The Buffer Setup page contains the parameters for the receive and retry buffers.
Table 3–4
31:3
<5–1>:0
Value
Value
describes the parameters you can set on this page.
2.1. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.
Used as an offset from the address contained in one of the function’s Base Address
registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are
set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.
Indicates which of a function’s Base Address registers, located beginning at 0x10 in
configuration space, is used to map the function’s MSI-X PBA into memory space.
This field is read-only.
Specifies the maximum payload size supported. This parameter sets the read-only
value of the max payload size supported field of the device capabilities register
(0x084[2:0]) and optimizes the IP core for this size payload. The SOPC Builder
design flow supports only maximum payload sizes of 128 bytes and 256 bytes. The
maximum payload size varies for different devices.
Specifies the number of virtual channels supported. This parameter sets the
read-only extended virtual channel count field of port virtual channel capability
register 1 and controls how many virtual channel transaction layer interfaces are
implemented. The number of virtual channels supported depends upon the
configuration, as follows:
Specifies the number of virtual channels in the low-priority arbitration group. The
virtual channels numbered less than this value are low priority. Virtual channels
numbered greater than or equal to this value are high priority. Refer to
Virtual Channel Arbitration” on page 4–10
the read-only low-priority extended virtual channel count field of the port virtual
channel capability register 1.
Controls automatic configuration of the retry buffer based on the maximum payload
size. For the hard IP implementation, this is set to On.
Sets the size of the retry buffer for storing transmitted PCI Express packets until
acknowledged. This option is only available if you do not turn on Auto configure
retry buffer size. The hard IP retry buffer is fixed at 4 KBytes for Arria II GX and
Cyclone IV GX devices, at 16 KBytes for Stratix IV GX devices, and at 8 KBytes for
Stratix V GX devices.
Hard IP: 1–2 channels for Stratix IV GX devices, 1 channel for Arria II GX,
Cyclone IV GX, and Stratix V GX devices
Soft IP: 2 channels
SOPC Builder: 1 channel
Description
Description
for more information. This parameter sets
December 2010 Altera Corporation
Chapter 3: Parameter Settings
PCI Express Base
“Transmit
Buffer Setup