IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 266

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

15–38
Table 15–28. ebfm_cfgwr_imm_nowt Procedure (Part 2 of 2)
Table 15–29. ebfm_cfgrd_wait Procedure
PCI Express Compiler User Guide
Arguments
Location
Syntax
Arguments
bus_num
dev_num
fnc_num
regb_ad
regb_ln
imm_data
ebfm_cfgrd_wait(bus_num, dev_num, fnc_num, regb_ad, regb_ln, lcladdr, compl_status)
bus_num
dev_num
fnc_num
regb_ad
regb_ln
lcladdr
compl_status
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_cfgrd_wait Procedure
The ebfm_cfgrd_wait procedure reads up to four bytes of data from the specified
configuration register and stores the data in BFM shared memory. This procedure
waits until the read completion has been returned.
PCI Express bus number of the target device.
PCI Express device number of the target device.
Function number in the target device to be accessed.
Byte-specific address of the register to be written.
Length, in bytes, of the data written. Maximum length is four bytes, The regb_ln the
regb_ad arguments cannot cross a DWORD boundary.
Data to be written
In VHDL. this argument is a std_logic_vector(31 downto 0).
In Verilog HDL, this argument is reg [31:0].
In both languages, the bits written depend on the length:
Length
PCI Express bus number of the target device.
PCI Express device number of the target device.
Function number in the target device to be accessed.
Byte-specific address of the register to be written.
Length, in bytes, of the data read. Maximum length is four bytes. The regb_ln and the
regb_ad arguments cannot cross a DWORD boundary.
BFM shared memory address of where the read data should be placed.
Completion status for the configuration transaction.
In VHDL, this argument is a std_logic_vector(2 downto 0) and is set by the
procedure on return.
In Verilog HDL, this argument is reg [2:0].
In both languages, this is the completion status as specified in the PCI Express
specification:
4
3
2
1
Compl_StatusDefinition
000SC— Successful completion
001UR— Unsupported Request
010CRS — Configuration Request Retry Status
100CA — Completer Abort
Bits Written
[31:0]
[23:0]
[15:0]
[7:0]
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
BFM Procedures and Functions