IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 26

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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PCI Express Compiler User Guide
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After you purchase a license for the PCI Express IP core, you can request a license file
from the Altera licensing website at (www.altera.com/licensing) and install it on your
computer. When you request a license file, Altera emails you a license.dat file. If you
do not have internet access, contact your local Altera representative.
With Altera's free OpenCore Plus evaluation feature, you can perform the following
actions:
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OpenCore Plus hardware evaluation is not applicable to the hard IP implementation
of the PCI Express Compiler. You can use the hard IP implementation of this IP core
without a separate license.
For information about IP core verification, installation and licensing, and evaluation
using the OpenCore Plus feature, refer to the
Megafunctions.
For details on installation and licensing, refer to the
Licensing
OpenCore Plus hardware evaluation supports the following two operation modes:
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All IP cores in a device time out simultaneously when the most restrictive evaluation
time is reached. If your design includes more than one megafunction, a specific IP
core's time-out behavior may be masked by the time-out behavior of the other IP
cores.
For IP cores, the untethered timeout is one hour; the tethered timeout value is
indefinite. Your design stops working after the hardware evaluation time expires.
During time-out the Link Training and Status State Machine (LTSSM) is held in the
reset state.
Simulate the behavior of an IP core (Altera IP core or AMPP
your system
Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
Generate time-limited device programming files for designs that include IP cores
Program a device and verify your design in hardware
Untethered—the design runs for a limited time.
Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
Manual.
OpenCore Plus Evaluation of
OpenCore Plus Evaluation (Not Required for Hard IP)
Altera Software Installation and
December 2010 Altera Corporation
SM
megafunction) in
Chapter 1: Datasheet