IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 104
![IP CORE - PCI Express X1 And X4 Lanes For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/4
Manufacturer Part Number
IP-AGX-PCIE/4
Description
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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5–20
Figure 5–21. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-DWord Header TLP with QWord Aligned Address
Figure 5–22. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-DWord Header TLP with non-QWord Aligned Address
PCI Express Compiler User Guide
tx_st_data[127:96]
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_data[31:0]
Figure 5–21
for a four dword header TLP with qword aligned data.
Figure 5–22
for a four dword header TLP with non-qword aligned addresses. In this example,
tx_st_empty is low because the data ends in the upper 64 bits of tx_st_data.
tx_st_empty
tx_st_empty
tx_st_valid
tx_st_eop
tx_st_sop
tx_st_eop
tx_st_sop
clk
clk
shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
Header 3
Header 2
Header 1
Header 0
Header 2
Header 1
Header 0
Header 3
Data 2
Data 1
Data 0
Data 2
Data 1
Data 0
Data 3
Data n-1
Data n-2
Data n
Data 4
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface
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