IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 199

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 11: Flow Control
Throughput of Non-Posted Reads
December 2010 Altera Corporation
1
Nevertheless, maintaining maximum throughput of completion data packets is
important. PCI Express endpoints must offer an infinite number of completion
credits. The PCI Express IP core must buffer this data in the RX buffer until the
application can process it. Because the PCI Express IP core is no longer managing the
RX buffer through the flow control mechanism, the application must manage the RX
buffer by the rate at which it issues read requests.
To determine the appropriate settings for the amount of space to reserve for
completions in the RX buffer, you must make an assumption about the length of time
until read completions are returned. This assumption can be estimated in terms of an
additional delay, beyond the FC Update Loop Delay, as discussed in the section
“Throughput of Posted Writes” on page
completions are not exactly the same as those for the posted writes and FC Updates in
the PCI Express logic. However, the delay differences are probably small compared
with the inaccuracy in the estimate of the external read to completion delays.
Assuming there is a PCI Express switch in the path between the read requester and
the read completer and assuming typical read completion times for root ports,
Table 11–3
transaction’s round trip delay.
Table 11–3. Completion Data Space (in Credit units) to Cover Read Round Trip Delay
Note also that the completions can be broken up into multiple completions of smaller
packet size.
With multiple completions, the number of available credits for completion headers
must be larger than the completion data space divided by the maximum packet size.
Instead, the credit space for headers must be the completion data space (in bytes)
divided by 64, because this is the smallest possible read completion boundary. Setting
the Desired performance for received completions to High on the Buffer Setup page
when specifying parameter settings in your IP core configures the RX buffer with
enough space to meet the above requirements. You can adjust the Desired
performance for received completions up or down from the High setting to tailor the
RX buffer size to your delays and required performance.
Max Packet Size
1024
2048
4096
128
256
512
shows the estimated completion space required to cover the read
×8 Function
Typical
120
144
192
256
384
768
11–1. The paths for the read requests and the
×4 Function
Typical
112
160
256
384
768
96
PCI Express Compiler User Guide
×1 Function
Typical
128
192
384
768
56
80
11–5