IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 235

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Chaining DMA Design Example
December 2010 Altera Corporation
1
The chaining DMA design example requires setting BAR 2 or BAR 3 to a minimum of
256 bytes. To run the DMA tests using MSI, you must set the MSI messages requested
parameter on the Capabilities page to at least 2.
The chaining DMA design example uses an architecture capable of transferring a
large amount of fragmented memory without accessing the DMA registers for every
memory block. For each block of memory to be transferred, the chaining DMA design
example uses a descriptor table containing the following information:
■
■
■
■
The BFM driver writes the descriptor tables into BFM shared memory, from which the
chaining DMA design engine continuously collects the descriptor tables for DMA
read, DMA write, or both. At the beginning of the transfer, the BFM programs the
endpoint chaining DMA control register. The chaining DMA control register indicates
the total number of descriptor tables and the BFM shared memory address of the first
descriptor table. After programming the chaining DMA control register, the chaining
DMA engine continuously fetches descriptors from the BFM shared memory for both
DMA reads and DMA writes, and then performs the data transfer for each descriptor.
Length of the transfer
Address of the source
Address of the destination
Control bits to set the handshaking behavior between the software application or
BFM driver and the chaining DMA module.
PCI Express Compiler User Guide
15–7