IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 231

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Endpoint Testbench
Figure 15–1. Testbench Top-Level Module for Endpoint Designs
December 2010 Altera Corporation
Testbench Top Level (<variation name>_testbench)
<variation name>_example_
chaining_pipen1b.v
Endpoint Example Design
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces
of the root port and endpoints or the serial PCI Express interface. The testbench
design does not allow more than one PCI Express link to be simulated at a time.
Figure 15–1
The top-level of the testbench instantiates four main modules:
■
■
■
■
In addition, the testbench has routines that perform the following tasks:
<variation name>_example_chaining_pipen1b—This is the example endpoint
design that includes your variation of the IP core variation. For more information
about this module, refer to
altpcietb_bfm_rp_top_x8_pipen1b—This is the root port PCI Express BFM. For
detailed information about this module, refer
altpcietb_pipe_phy—There are eight instances of this module, one per lane. These
modules interconnect the PIPE MAC layer interfaces of the root port and the
endpoint. The module mimics the behavior of the PIPE PHY layer to both MAC
interfaces.
altpcietb_bfm_driver_chaining—This module drives transactions to the root port
BFM. This is the module that you modify to vary the transactions sent to the
example endpoint design or your own design. For more information about this
module, refer to
■
■
Generates the reference clock for the endpoint at the required frequency.
Provides a PCI Express reset at start up.
presents a high level view of the testbench.
“Root Port Design Example” on page
PIPE Interconnection
(altpcierd_pipe_phy)
Module (x8)
“Chaining DMA Design Example” on page
(altpcietb_bfm_rp_top_x8_pipen1b)
(altpcietb_bfm_driver_chaining)
Test Driver Module
to“Root Port BFM” on page
Chaining DMA
Root Port BFM
15–22.
PCI Express Compiler User Guide
15–6.
15–26.
15–3