IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 251

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port Design Example
Figure 15–5. Root Port Design Example
December 2010 Altera Corporation
(altpcietb_bfm_
Test Driver
driver_rp.v)
■
You can use the example root port design for Verilog HDL simulation. All of the
modules necessary to implement the example design with the variation file are
contained in <variation_name>_example_rp_pipen1b.v. This file is created in the
<variation_name>_examples/root_port subdirectory of your project when the PCI
Express IP core variant is generated.
The MegaWizard interface creates the variation files in the top-level directory of your
project, including the following files:
■
■
■
■
The following modules are generated for the design example in the subdirectory
<variation_name>_examples/root_port:
<var> _example_rp_pipen1b.v
Test Driver (altpcietb_bfm_driver_rp.v)—the chaining DMA endpoint test driver
which configures the root port and endpoint for DMA transfer and checks for the
successful transfer of data. Refer to the
detailed description.
<variation_name>.v—the top level file of the PCI Express IP core variation. The file
instantiates the SERDES and PIPE interfaces, and the parameterized core,
<variation_name>_core.v.
<variation_name>_serdes.v —contains the SERDES.
<variation_name>_core.v—used in synthesizing <variation_name>.v.
<variation_name>_core.vo—used in simulating <variation_name>.v.
Root Port BFM Tasks and Shared Memory
(altpcietb_bfm_shmem)
BFM Shared Memory
VC1 Avalon-ST Interface
VC0 Avalon-ST Interface
(altpcietb_bfm_vcintf_ast)
(altpcietb_bfm_vcintf_ast)
BFM Log Interface
(altpcietb_bfm_log)
BFM Read/Write Shared
Request Procedures
(altpcietb_bfm_rdwr)
cfg_sample.v)
(altpcietb_tl_
Config Bus
Avalon-ST
Avalon-ST
“Test Driver Module” on page 15–18
(variation_name.v)
(altpcietb_bfm_configure)
BFM Request Interface
(altpcietb_bfm_req_intf)
BFM Configuration
PCI Express
Root Port
Variation
Procedures
PCI Express Compiler User Guide
PCI Express
for a
15–23