IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 207

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Dynamic Reconfiguration
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
1
This chapter describes features of the PCI Express IP core that you can use to
reconfigure the core after power-up. It includes the following sections:
■
■
The PCI Express IP core reconfiguration block allows you to dynamically change the
value of configuration registers that are read-only at run time.The PCI Express
reconfiguration block is only available in the hard IP implementation for the
Arria II GX, Cyclone IV GX, HardCopy IV GX and Stratix IV GX devices. Access to
the PCI Express reconfiguration block is available when you select Enable for the
PCIe Reconfig option on the System Settings page using the parameter editor. You
access this block using its Avalon-MM slave interface. For a complete description of
the signals in this interface, refer to
Hard IP Implementation” on page
The PCI Express reconfiguration block provides access to read-only configuration
registers, including configuration space, link configuration, MSI and MSI-X
capabilities, power management, and advanced error reporting.
The procedure to dynamically reprogram these registers includes the following three
steps:
1. Bring down the PCI Express link by asserting the pcie_reconfig_rstn reset signal,
2. Reprogram configuration registers using the Avalon-MM slave PCIe Reconfig
3. Release the npor reset signal.
You can use the LMI interface to change the values of configuration registers that are
read/write at run time. For more information about the LMI interface, refer to
Signals—Hard IP Implementation” on page
Dynamic Reconfiguration
Transceiver Offset Cancellation
if the link is already up. (Reconfiguration can occur before the link has been
established.)
interface.
5–41.
“PCI Express Reconfiguration Block Signals—
13. Reconfiguration and Offset
5–40.
PCI Express Compiler User Guide
Cancellation
“LMI