IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 209

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 13: Reconfiguration and Offset Cancellation
Dynamic Reconfiguration
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 2 of 7)
December 2010 Altera Corporation
Address
Bits
14:12
11:9
8:6
3
4
5 Extended TAG field supported.
Surprise Down error reporting capabilities.
(Available in PCI Express Base Specification Revision 1.1
compliant Cores, only.)
Downstream Port. This bit must be set to 1 if the
component supports the optional capability of detecting
and reporting a Surprise Down error condition.
Upstream Port. For upstream ports and components
that do not support this optional capability, this bit must
be hardwired to 0.
Data Link Layer active reporting capabilities.
(Available in PCI Express Base Specification Revision 1.1
compliant Cores, only.)
Downstream Port: This bit must be set to 1 if the
component supports the optional capability of reporting
the DL_Active state of the Data Link Control and
Management state machine.
Upstream Port: For upstream ports and components that
do not support this optional capability, this bit must be
hardwired to 0.
Endpoint L0s acceptable latency. The following encodings
are defined:
Endpoint L1 acceptable latency. The following encodings
are defined:
These bits record the presence or absence of the attention
and power indicators.
b’000 – Maximum of 64 ns.
b’001 – Maximum of 128 ns.
b’010 – Maximum of 256 ns.
b’011 – Maximum of 512 ns.
b’100 – Maximum of 1 µs.
b’101 – Maximum of 2 µs.
b’110 – Maximum of 4 µs.
b’111– No limit.
b’000 – Maximum of 1 µs.
b’001 – Maximum of 2 µs.
b’010 – Maximum of 4 µs.
b’011 – Maximum of 8 µs.
b’100 – Maximum of 16 µs.
b’101 – Maximum of 32 µs.
b’110 – Maximum of 64 µs.
b’111 – No limit.
[0]: Attention button present on the device.
[1]: Attention indicator present for an endpoint.
[2]: Power indicator present for an endpoint.
Description
Default
Value
b’000
b’000
b’000
b’0
b’0
b’0
PCI Express Compiler User Guide
Table 6–8 on page
Link Capability register
Table 6–8 on page
Link Capability register
Table 6–8 on page
Device Capability
register
Table 6–8 on page
Device Capability
register
Table 6–8 on page
Device Capability
register
Table 6–8 on page
Slot Capability register
Additional Information
6–5,
6–5,
6–5,
6–5,
6–5,
6–5,
13–3