IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 196

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

11–2
Figure 11–1. Flow Control Update Loop
PCI Express Compiler User Guide
Layer
App
1
Control
Check)
Gating
(Credit
Logic
Flow
Allow
Transaction
Each receiver also maintains a credit allocated counter which is initialized to the
total available space in the RX buffer (for the specific Flow Control class) and then
incremented as packets are pulled out of the RX buffer by the application layer. The
value of this register is sent as the FC Update DLLP value.
The following numbered steps describe each step in the Flow Control Update loop.
The corresponding numbers on
correspond.
1. When the application layer has a packet to transmit, the number of credits
2. After the packet is selected for transmission the credits consumed register is
3. The packet is received at the other end of the link and placed in the RX buffer.
4. At some point the packet is read out of the RX buffer by the application layer. After
5. The value in the credit allocated register is used to create an FC Update DLLP.
Layer
Data Source
Consumed
required is calculated. If the current value of the credit limit minus credits
consumed is greater than or equal to the required credits, then the packet can be
transmitted immediately. However, if the credit limit minus credits consumed is
less than the required credits, then the packet must be held until the credit limit is
increased to a sufficient value by an FC Update DLLP. This check is performed
separately for the header and data credits; a single packet consumes only a single
header credit.
incremented by the number of credits consumed by this packet. This increment
happens for both the header and data credit consumed registers.
the entire packet is read out of the RX buffer, the credit allocated register can be
incremented by the number of credits the packet has used. There are separate
credit allocated registers for the header and data credits.
Counter
2
Credits
Credit
Limit
Incr
Data Link
7
Update
Decode
DLLP
Layer
FC
Data Packet
Physical
Layer
FC Update DLLP
Express
Figure 11–1
Link
PCI
Physical
Layer
6
show the general area to which they
Data Link
Generate
Update
Layer
DLLP
FC
5
Data Sink
3
Allocated
Transaction
Credit
December 2010 Altera Corporation
Buffer
Layer
Rx
Throughput of Posted Writes
Incr
Chapter 11: Flow Control
4
Data Packet
Layer
App