IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 349

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
December 2010 Altera Corporation
Arria GX Devices
Cyclone III Family
Table C–11
Arria GX (EP1AGX60DF780C6) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 10.1.
Table C–11. Performance and Resource Utilization, Descriptor/Data Interface - Arria GX Devices
Table C–12
Cyclone III (EP3C80F780C6) devices for different parameters, using the Quartus II
software, version 10.1.
Table C–12. Performance and Resource Utilization, Descriptor/Data Interface - Cyclone III
Family
Note to
(1) Max payload set to 128 bytes, the number of Tags supported set to 4, and Desired performance for received
×1/ ×4
×1/ ×4
×1
requests and Desired performance for completions both set to Low.
×1
×1
×4
×4
×1
×1
×1
×4
×4
(1)
Table
shows the typical expected performance and resource utilization of
shows the typical expected performance and resource utilization of
C–12:
Clock (MHz)
Parameters
Clock (MHz)
Parameters
Internal
Internal
125
125
125
125
62.5
62.5
125
125
125
125
Channels
Virtual
Channels
Virtual
1
2
1
2
1
2
1
2
1
2
Combinational
Elements
ALUTs
122000
5200
6400
6800
8210
10100
10500
10200
Logic
8200
8500
Dedicated
Registers
Registers
3600
4500
3800
4600
4500
5300
Logic
3600
4400
4600
5400
Size
Size
PCI Express Compiler User Guide
M512
Memory Blocks
1
2
6
6
M9K Memory
Blocks
25
28
12
17
6
9
M4K
21
13
12
19
C–7