IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 25

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
OpenCore Plus Evaluation (Not Required for Hard IP)
OpenCore Plus Evaluation
December 2010 Altera Corporation
Table 1–9. Recommended Device Family Speed Grades (Part 2 of 2)
You can use Altera's free OpenCore Plus evaluation feature to evaluate the IP core in
simulation and in hardware before you purchase a license. You need to purchase a
license for the soft PCI Express IP core only after you are satisfied with its
functionality and performance, and you are ready to take your design to production.
Stratix II GX
Stratix III
Stratix IV GX Gen1
Stratix IV GX Gen2
Arria GX
Arria II GX
Cyclone II, Cyclone III
Cyclone IV GX
Stratix II
Stratix II GX
Stratix III
Stratix IV E Gen1
Stratix IV GX Gen1
Notes to
(1) The RX Buffer and Retry Buffer ECC options are only available in the hard IP implementation.
(2) This is a power-saving mode of operation.
(3) Final results pending characterization by Altera for speed grades -2, -3, and -4. Refer to the .fit.rpt file generated
(4) Closing timing for the –3 speed grades in the provided endpoint example design requires seed sweeping.
(5) Altera recommends the External PHY 16-bit SDR or 8-bit SDR modes in the -8 speed grade.
(6) Additional speed grades (-7) are pending characterization.
(7) You must turn on the following Physical Synthesis settings in the Quartus II Fitter Settings to achieve timing
(8) Altera recommends disabling the OpenCore Plus feature for the ×8 soft IP implementation because including this
by the Quartus II software.
closure for these speed grades and variations: Perform physical synthesis for combinational logic, Perform
register duplication, and Perform register retiming. In addition, you can use the Quartus II Design Space
Explorer or Quartus II seed sweeping methodology. Refer to the
chapter in volume 1 of the Quartus II Development Software Handbook for more information about how to set
these options.
feature makes it more difficult to close timing.
Table
Device Family
1–9:
Avalon-ST or Descriptor/Data Interface Soft IP Implementation
(Not Required for Hard IP)
×1, ×4
×1, ×4
×1
×1, ×4
×1
×1, ×4
×1, ×4
×1, ×4
×1
×1
×1, ×4
×1
×1, ×4
×8
×1, ×4
×1
×1
×1, ×4
×1
×4
Link Width
Netlist Optimizations and Physical Synthesis
Frequency (MHz)
Internal Clock
62.5
62.5
62.5
62.5
62.5
62.5
125
125
125
125
125
125
125
125
125
125
250
125
125
125
PCI Express Compiler User Guide
–3, –4, –5
-2, -3, -4
-2, -3, -4
-2, -3, -4
-2, -3
–6
–4. –5
–6
–6, –7, –8
–6, –7
–3, –4, –5
–3, –4, –5
–3, –4, –5
–3
–2, –3, –4
–2, –3, –4
all speed grades
all speed grades
all speed grades
all speed grades
Recommended
Speed Grades
(7)
(7) (8)
(7)
(7)
(7)
(7)
(7)
(7)
1–15