IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 142

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–58
Table 5–33. PIPE Interface Signals (Part 2 of 2)
Test Signals
PCI Express Compiler User Guide
phystatus<n>_ext
rxelecidle<n>_ext
rxstatus<n>_ext[2:0]
pipe_rstn
pipe_txclk
rate_ext
Note to
(1) where <n> is the lane number ranging from 0-7
(2) For variants that use the internal transceiver, these signals are for simulation only. For Quartus II software compilation, these pipe signals can
be left floating.
Table
Signal SOPC Builder
5–33:
c
(1) (2)
(1) (2)
The test_in and test_out busses provide run-time control and monitoring of the
internal state of the IP cores.
implementation.
Altera recommends that you use the test_out and test_in signals for debug or non-
critical status monitoring purposes such as LED displays of PCIe link status. They
should not be used for design function purposes. Use of these signals will make it
more difficult to close timing on the design. The signals have not been rigorously
verified and will not function as documented in some corner cases.
The debug signals provided on test_out depend on the setting of test_in[11:8].
provides the encoding for test_in.
Table 5–34. Decoding of test_in[11:8]
test_in[11:8] Value
4’b0011
All other values
(1) (2)
I/O
O
O
O
I
I
I
Signal Group
PIPE Interface Signals
Reserved
PHY status <n>. This signal communicates completion of several PHY
requests.
Receive electrical idle <n>. This signal forces the receive output to
electrical idle.
Receive status <n>. This signal encodes receive status and error codes
for the receive data stream and receiver detection.
Asynchronous reset to external PHY. This signal is tied high and expects
a pull-down resistor on the board. During FPGA configuration, the pull-
down resistor resets the PHY and after that the FPGA drives the PHY out
of reset. This signal is only on IP cores configured for the external PHY.
Transmit datapath clock to external PHY. This clock is derived from
refclk and it provides the source synchronous clock for the transmit
data of the PHY.
This signal is available for simulation purposes only in the hard IP
implementation.
When asserted, indicates the interface is operating at the 5.0 Gbps rate.
Table 5–35
describes the test signals for the hard IP
Description
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Test Signals